SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR STORAGE DEVICE

WIPO Patent Application WO/2010/082504

A1

Disclosed is an SOI-MISFET having excellent characteristics of low power consumption and high speed operation, wherein the area of elements is reduced. Specifically, an N conductivity type MISFET region and a P conductivity type MISFET region in an SOI-MISFET are formed to share one same diffusion layer region.  Meanwhile, well diffusion layers of the N conductivity type MISFET region and the P conductivity type MISFET region, to which a substrate potential is applied, are isolated from each other by an STI layer.  Since the diffusion layer regions of the N conductivity type MISFET region and the P conductivity type MISFET region, which serve as an output part of an CMISFET, are formed as one common region and directly connected by a metal silicide, the area of elements is reduced.

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TSUCHIYA RYUTA (JP)
SUGII NOBUYUKI (JP)
MORITA YUSUKE (JP)
YOSHIMOTO HIROYUKI (JP)
ISHIGAKI TAKASHI (JP)
KIMURA SHINICHIRO (JP)

PCT/JP2010/000236

July 22, 2010

January 18, 2010

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HITACHI LTD (JP)
TSUCHIYA RYUTA (JP)
SUGII NOBUYUKI (JP)
MORITA YUSUKE (JP)
YOSHIMOTO HIROYUKI (JP)
ISHIGAKI TAKASHI (JP)
KIMURA SHINICHIRO (JP)

H01L29/786; H01L21/28; H01L21/336; H01L21/8238; H01L21/8244; H01L27/08; H01L27/092; H01L27/11; H01L29/423; H01L29/49

WO2007004535A1

2007-01-11

JP2003078141A	2003-03-14
JP2008288269A	2008-11-27

POLAIRE I. P. C. (JP)
Polaire Intellectual Property Corporation (JP)

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