Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2018/020713
Kind Code:
A1
Abstract:
A semiconductor device (300) is provided with: an active layer (311a), which is an active layer inside of a SOI substrate, and in which an element constituting a circuit is formed; an embedded insulating layer (311b), which is an embedded insulating layer inside of the SOI substrate, and is in contact with the active layer (311a); a deep trench isolation (DTI) region (302), which is formed in the active layer (311a) so as to surround the whole periphery of a forming region of the element in plan view, and which reaches the rear surface of the active layer (311a) from the front surface thereof; and a first conductive film (310) formed above the element. The DTI region (302) has a first hole (303) inside of the DTI region (302), and the thickness of the first conductive film (310) is more than that of the active layer (311a).
Inventors:
NATSUME SHINYA
INOUE MASAKI
TANAKA MITSUO
INOUE MASAKI
TANAKA MITSUO
Application Number:
PCT/JP2017/006107
Publication Date:
February 01, 2018
Filing Date:
February 20, 2017
Export Citation:
Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H01L21/02; H01L21/3205; H01L21/76; H01L21/762; H01L21/768; H01L21/822; H01L21/8222; H01L23/29; H01L23/31; H01L23/522; H01L27/04; H01L27/06; H01L27/12
Foreign References:
| US20020182780A1 | 2002-12-05 | |||
| JP2011151121A | 2011-08-04 | |||
| JP2013222838A | 2013-10-28 | |||
| JP2006049828A | 2006-02-16 | |||
| JP2009016542A | 2009-01-22 | |||
| JP2009076782A | 2009-04-09 | |||
| JP2009105269A | 2009-05-14 | |||
| JPS61251157A | 1986-11-08 | |||
| JPH0373558A | 1991-03-28 | |||
| US20120261747A1 | 2012-10-18 |
Attorney, Agent or Firm:
KAMATA Kenji et al. (JP)
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