Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2019/151024
Kind Code:
A1
Abstract:
The present invention provides a method for manufacturing a semiconductor device, the method comprising: a first step for preparing, in a bottom section of a recess part of an insulation layer, an intermediate body provided with a base body composed of a material (insulator) having an etching resistance to an etching material for the insulation layer; and a second step for embedding a conductive material such that the embedded conductive material is in contact with a side surface and an upper surface of the base body in the recess part of the insulation layer. According to this method, in a semiconductor device comprising a fin type FET, the conductive material embedded between semiconductor fins is aligned by being embedded in the recess part of the insulation layer, and thus a fixed potential line (power rail) composed of the conductive material can be easily formed.
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Inventors:
KIBI KAZUO (JP)
Application Number:
PCT/JP2019/001711
Publication Date:
August 08, 2019
Filing Date:
January 21, 2019
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
International Classes:
H01L21/336; H01L21/3065; H01L21/316; H01L21/3205; H01L21/768; H01L21/8238; H01L23/522; H01L27/092; H01L29/41; H01L29/417; H01L29/78
Domestic Patent References:
| WO2013111592A1 | 2013-08-01 | |||
| WO2017208807A1 | 2017-12-07 |
Foreign References:
| JPH0371666A | 1991-03-27 | |||
| US20170062421A1 | 2017-03-02 | |||
| US20150287795A1 | 2015-10-08 | |||
| JP2017208469A | 2017-11-24 | |||
| JP2011129771A | 2011-06-30 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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