Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2022/249855
Kind Code:
A1
Abstract:
This semiconductor device comprises a power transistor UMOS, an n-type transistor NMOS, and a p-type transistor PMOS on a stacked semiconductor substrate SB comprising an n-type semiconductor substrate SUB having an n-type drift layer DL, a p-type embedded base layer BBL, and a p-type base layer BL stacked thereon. The power transistor UMOS includes a trench gate electrode EGU extending through the base layer BL. The p-type transistor PMOS is formed in an n-type well region NW formed in the base layer BL. The n-type transistor NMOS is formed in the base layer BL or in a p-type well region further formed in the n-type well region. The p-type impurity concentration of the embedded channel region EBC of the p-type transistor PMOS is equal to the p-type impurity concentration of the base layer BL.
Inventors:
OKAMOTO MITSUO (JP)
YAO ATSUSHI (JP)
SATO HIROSHI (JP)
HARADA SHINSUKE (JP)
YAO ATSUSHI (JP)
SATO HIROSHI (JP)
HARADA SHINSUKE (JP)
Application Number:
PCT/JP2022/019342
Publication Date:
December 01, 2022
Filing Date:
April 28, 2022
Export Citation:
Assignee:
AIST (JP)
International Classes:
H01L29/78; H01L21/336; H01L21/76; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L29/06; H01L29/12
Foreign References:
| JP2000022140A | 2000-01-21 | |||
| JP2002313945A | 2002-10-25 | |||
| JP2004173292A | 2004-06-17 | |||
| JP2009088220A | 2009-04-23 | |||
| US20070298563A1 | 2007-12-27 |
Other References:
OKAMOTO MITSUO; YAO ATSUSHI; SATO HIROSHI; HARADA SHINSUKE: "First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer", 2021 33RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), THE INSTITUTE OF ELECTRICAL ENGINEERING OF JAPAN, 30 May 2021 (2021-05-30), pages 71 - 74, XP033925016, DOI: 10.23919/ISPSD50666.2021.9452262
Attorney, Agent or Firm:
TSUTSUI & ASSOCIATES (JP)
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