Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/027721
Kind Code:
A1
Abstract:
Mesa regions between adjacent trenches (2), each of which is formed within an n--type drift layer (1) and is internally provided with a first gate electrode (4a) with a first gate insulating film (3a) being interposed therebetween, are provided with a p-type base region (5) and a floating p+-type region (10) that are separated from each other by the trenches (2), said floating p+-type region (10) having a surface that is partially covered by a second gate electrode (4b) with a second gate insulating film (3b) being interposed therebetween. An emitter electrode (9) is in contact with the p-type base region (5) and an n+-type emitter region (6), and is electrically insulated from the first and second gate electrodes (4a, 4b) and the floating p+-type region (10) by a portion of the floating p+-type region (10) not covered by the second gate electrode (4b) and an interlayer insulating film (9) that covers the first and second gate electrodes (4a, 4b). Consequently, controllability of turn-on dV/dt by the gate resistance Rg is able to be improved.
Inventors:
KOBAYASHI YUSUKE (JP)
ONOZAWA YUICHI (JP)
TAKEI MANABU (JP)
NAKAGAWA AKIO (JP)
ONOZAWA YUICHI (JP)
TAKEI MANABU (JP)
NAKAGAWA AKIO (JP)
Application Number:
PCT/JP2015/072651
Publication Date:
February 25, 2016
Filing Date:
August 10, 2015
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L29/78; H01L21/336; H01L29/739
Foreign References:
| JP2014053409A | 2014-03-20 | |||
| JP2012151470A | 2012-08-09 | |||
| JP2011243946A | 2011-12-01 | |||
| JP2002190595A | 2002-07-05 | |||
| JP2001177091A | 2001-06-29 |
Attorney, Agent or Firm:
SAKAI, AKINORI (JP)
Akinori Sakai (JP)
Akinori Sakai (JP)
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