Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/155782
Kind Code:
A1
Abstract:
The present invention simplifies the formation of an isolation region of a semiconductor substrate having an increased film thickness. This semiconductor device is provided with: an element region, a wiring region, an external connection unit, a front surface side isolation region, and a rear surface side isolation region. The element region is formed in the semiconductor substrate. A wiring layer is arranged on one surface of the semiconductor substrate and is electrically connected to the element region. The external connection unit is electrically connected to the wiring layer. The front surface side isolation region is arranged surrounding the external connection unit and is formed from the surface at which the wiring region is arranged on the semiconductor substrate, to a depth near a central part of the semiconductor substrate. The rear surface side isolation region is arranged surrounding the external connection unit and is formed from a surface of the semiconductor substrate that differs from the surface at which the wiring region is arranged, to a depth adjacent to the bottom part of the front surface side isolation region.
Inventors:
KAWABATA KAZUYA (JP)
KUDOU TOMOAKI (JP)
CHIBA YOHEI (JP)
KUDOU TOMOAKI (JP)
CHIBA YOHEI (JP)
Application Number:
PCT/JP2018/048008
Publication Date:
August 15, 2019
Filing Date:
December 27, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146; H01L21/76; H04N5/369
Domestic Patent References:
| WO2017018216A1 | 2017-02-02 | |||
| WO2017130723A1 | 2017-08-03 |
Foreign References:
| JP2015076569A | 2015-04-20 | |||
| US20170141145A1 | 2017-05-18 | |||
| US20100181635A1 | 2010-07-22 | |||
| JP2014116472A | 2014-06-26 | |||
| JP2015065269A | 2015-04-09 | |||
| US20120009720A1 | 2012-01-12 |
Attorney, Agent or Firm:
MATSUO Kenichiro (JP)
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