Title:
SEMICONDUCTOR DEVICE AND METHOD FOR PREVENTING APPLICATION OF NEGATIVE POTENTIAL
Document Type and Number:
WIPO Patent Application WO/2016/080123
Kind Code:
A1
Abstract:
To improve quality by preventing a malfunction.
This semiconductor device (1) is provided with internal circuits (1-1 to 1-n) and resistors (R1 to Rn). The internal circuits (1-1 to 1-n) are mounted within the semiconductor device (1). The resistors (R1 to Rn) are arranged between the internal circuits (1-1 to 1-n) and a path (3a) that is connected to a ground terminal (1a) which grounds the semiconductor device (1). The path (3a) is a line through which a reverse current flows from the ground terminal (1a) toward an output terminal (1b) of the semiconductor device (1) if the output terminal (1b) is at a negative potential. One end of each of the resistors (R1 to Rn) is connected to the path (3a), and the other ends of the resistors (R1 to Rn) are connected to ground parts (2-1 to 2-n) of the internal circuits (1-1 to 1-n).
Inventors:
NAKAGAWA SHOU (JP)
Application Number:
PCT/JP2015/079287
Publication Date:
May 26, 2016
Filing Date:
October 16, 2015
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L21/822; H01L27/04; H01L27/06; H03K17/16; H03K17/695
Foreign References:
| JP2012034079A | 2012-02-16 | |||
| JP2009010477A | 2009-01-15 | |||
| JPH0690520A | 1994-03-29 | |||
| JP2013146008A | 2013-07-25 |
Attorney, Agent or Firm:
HATTORI, KIYOSHI (JP)
Kiyoshi Hattori (JP)
Kiyoshi Hattori (JP)
Download PDF: