Title:
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2015/068251
Kind Code:
A1
Abstract:
This semiconductor device has: an inter-layer insulating film (INS2); neighboring Cu wiring (M1W) formed within the inter-layer insulating film (INS2); and an insulating barrier film (BR1) that contacts the surface of the Cu wiring (M1W) and the surface of the inter-layer insulating film (INS2) and that covers the Cu wiring (M1W) and the inter-layer insulating film (INS2). Also, between the neighboring Cu wiring (M1W), the inter-layer insulating film (INS2) has a damage layer (DM1) at the surface thereof, and at a deeper position than the damage layer (DM1), has an electric field limiting layer (ER1) having a higher concentration of nitrogen than that of the damage layer (DM1).
Inventors:
USAMI TATSUYA (JP)
MIURA YUKIO (JP)
TSUCHIYA HIDEAKI (JP)
MIURA YUKIO (JP)
TSUCHIYA HIDEAKI (JP)
Application Number:
PCT/JP2013/080195
Publication Date:
May 14, 2015
Filing Date:
November 08, 2013
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP (JP)
International Classes:
H01L21/321; H01L21/768
Foreign References:
| JP2006128591A | 2006-05-18 | |||
| JP2006525651A | 2006-11-09 | |||
| JP2003229481A | 2003-08-15 | |||
| JP2010272826A | 2010-12-02 | |||
| JP2005302811A | 2005-10-27 |
Other References:
F. ITO ET AL.: "Effective Cu Surface Pre-treatment for High-reliable 22 nm-node Cu Dual Damascene Interconnects with High Plasma resistant Ultra Low-k Dielectric (k = 2.2", ADVANCED METALIZATION CONFERENCE, 5 October 2010 (2010-10-05)
See also references of EP 3067920A4
See also references of EP 3067920A4
Attorney, Agent or Firm:
TSUTSUI, Yamato et al. (JP)
Tsutsui Daiwa (JP)
Tsutsui Daiwa (JP)
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