Title:
SEMICONDUCTOR DEVICE FOR POWER AMPLIFICATION
Document Type and Number:
WIPO Patent Application WO/2023/188970
Kind Code:
A1
Abstract:
A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); a gate finger (42); and a drain finger (52). The semiconductor layer (20) in plan view is divided into an active region and an element isolation region (30). In plan view, a channel region comprises a plurality of unit channel regions (90) that are divided by the element isolation region (30) and are arranged in the Y-axis direction. The source electrode (60) comprises a plurality of unit source electrodes respectively facing the plurality of unit channel regions (90). A plurality of unit source regions (92) respectively including the plurality of unit source electrodes comprise one or more source vias (70) that include a conductor therein that is in contact with the lower surface electrode (64). In plan view, the side length of a minimum rectangular region enclosing the one or more source vias (70) is greater in the X-axis direction than in the Y-axis direction.
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Inventors:
KAWASHIMA KATSUHIKO
KATOU YOSHIAKI
MOTOYOSHI KANAME
KATOU YOSHIAKI
MOTOYOSHI KANAME
Application Number:
PCT/JP2023/005730
Publication Date:
October 05, 2023
Filing Date:
February 17, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/778; H01L21/338; H01L29/812
Foreign References:
| JP2020027912A | 2020-02-20 | |||
| JPH10144913A | 1998-05-29 | |||
| JP2022029417A | 2022-02-17 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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