Title:
SEMICONDUCTOR DEVICE PRODUCTION METHOD
Document Type and Number:
WIPO Patent Application WO/2020/229915
Kind Code:
A1
Abstract:
The present invention provides a semiconductor device with little variation in transistor characteristics. The present invention comprises: forming a first insulating body; forming an island-like laminate by laminating, upon the first insulating body, a first oxide, a second oxide, and a first conductor in that order; forming a second insulating body upon the first insulating body and the laminate; forming an opening in the second insulating body that exposes the laminate; removing a region of the first conductor exposed inside the opening so as to expose the upper surface of the second oxide, forming a second conductor and a third conductor that are disposed upon the second oxide, and then performing a washing treatment; forming a first oxide film that is exposed inside the opening, and is in contact with the side surface of the first oxide and the upper surface and side surface of the second oxide; performing a treatment for adding, via the first oxide film, oxygen to the vicinity of the interface between the second oxide and the first oxide film, and then performing a heating treatment; and forming, upon the first oxide film, a first insulating film and a first electroconductive film, and then performing a chemical polishing treatment so as to partially remove the first electroconductive film, the first insulating film, the first oxide film, and the second insulating body and expose the second insulating body, and forming a fourth conductor, a third insulating body, and a third oxide inside the opening provided in the second insulating body.
Inventors:
YAMAZAKI SHUNPEI (JP)
MURAKAWA TSUTOMU (JP)
SASAGAWA SHINYA (JP)
YAMADE NAOTO (JP)
HAMADA TAKASHI (JP)
KOMAGATA HIROKI (JP)
MURAKAWA TSUTOMU (JP)
SASAGAWA SHINYA (JP)
YAMADE NAOTO (JP)
HAMADA TAKASHI (JP)
KOMAGATA HIROKI (JP)
Application Number:
PCT/IB2020/053913
Publication Date:
November 19, 2020
Filing Date:
April 27, 2020
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
H01L21/336; H01L29/786; H01L21/8234; H01L21/8239; H01L21/8242; H01L27/088; H01L27/105; H01L27/108; H01L27/1156; H01L29/788; H01L29/792
Domestic Patent References:
| WO2019025911A1 | 2019-02-07 |
Foreign References:
| JP2019047020A | 2019-03-22 | |||
| JP2017050530A | 2017-03-09 | |||
| JP2016021559A | 2016-02-04 |
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