SEMICONDUCTOR DEVICE AND STACKED-TYPE SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2011/102100

A1

In a semiconductor device (1) according to the present invention, a solder resist (8) has a plurality of openings (8a-8f) that expose electrodes (5a-5f). Solder bumps (9a- 9f) are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate (6) and board electrodes (10a- lOf) of a printed wiring board (11) on which the semiconductor device (1) is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints.

WO/2002/095879	A HIGH FREQUENCY, LOW COST PACKAGE FOR SEMICONDUCTOR DEVICES
JP3847602	LAMINATED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND MOTHER BOARD AND MANUFACTURING METHOD THEREFOR

FUJISAWA YOSHITOMO (JP)

PCT/JP2011/000742

August 25, 2011

February 10, 2011

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CANON KK (JP)
FUJISAWA YOSHITOMO (JP)

H01L25/10; H01L21/48; H01L23/00; H01L23/498; H05K3/34

US6750549B1	2004-06-15
US6271109B1	2001-08-07
US20040227236A1	2004-11-18
US6936922B1	2005-08-30
JP3291368B2	2002-06-10
JP2010032321A	2010-02-12

ABE, Takuma et al. (30-2 Shimomaruko 3-chome, Ohta-k, Tokyo 01, JP)

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