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Title:
SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND ELECTRONIC EQUIPMENT
Document Type and Number:
WIPO Patent Application WO/2019/048967
Kind Code:
A1
Abstract:
Provided is a storage device in which the parasitic capacitance of a bit line has been reduced. The storage device comprises a sense amplifier that is electrically connected to a bit line, and a memory cell array that is layered upon the sense amplifier. The memory cell array comprises a plurality of memory cells. Each of the memory cells is electrically connected to the bit line. A bit line routing part is not provided within the memory cell array. Therefore, the bit line can be shortened, and the parasitic capacitance of the bit line is reduced.

Inventors:
ONUKI, Tatsuya (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
MATSUZAKI, Takanori (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
KATO, Kiyoshi (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
YAMAZAKI, Shunpei (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
Application Number:
IB2018/056412
Publication Date:
March 14, 2019
Filing Date:
August 24, 2018
Export Citation:
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Assignee:
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. (398 Hase, Atsugi-shi Kanagawa, 36, 〒2430036, JP)
International Classes:
H01L21/8242; G11C5/02; G11C11/4097; H01L21/336; H01L27/108; H01L27/1156; H01L29/786; H01L29/788; H01L29/792
Foreign References:
JP2015084411A2015-04-30
JP2015228492A2015-12-17
JP2013065638A2013-04-11
JP2015187905A2015-10-29
JP2016212944A2016-12-15
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