TECHNICAL FIELD

The disclosure relates generally to the field of semiconductor devices; more specifically, the disclosure relates to a semiconductor device and a method for forming the semiconductor device on a substrate.

BACKGROUND

Generally, a semiconductor device is an electronic device whose functioning is based on electronic properties of a semiconductor material, such as Silicon (Si), Germanium (Ge), Galium Arsende and the like. The semiconductor device is manufactured either as an individual device or as an integrated circuit (IC) device. A well known semiconductor device is named as a metal oxide semiconductor field-effect transistor (MOSFET) that includes a drain terminal, a source terminal and a gate terminal. However, another well known semiconductor device with a partially improved performance, is named as a fin field-effect transistor (FinFET) which is a multigate device, is chosen instead of traditional MOSFETs. Such a FinFET device includes two or more gate terminals which lie on two, or three sides of a channel made by a source terminal and a drain terminal of the FinFET device, hence, the FinFET device manifests better electrical conduction properties, superior short-channel behavior, lower switching times, and higher current density in comparison to the known MOSFET device.

Currently, gate-all-around (GAA) nanosheet (NS)/nanowire (NW) devices have been proposed as an alternative to the FinFET devices or the FinFET -based complementary metal oxide semiconductor (CMOS) logic devices (e.g. as used in contemporary microprocessors, memory cells, etc.). A GAANS/NW device is similar in concept to a FinFET device except that multiple gates surround the channel on all sides, which results in partly improved performance over the FinFET device. System-on-a-chip (SoC) applications of CMOS technology require the co integration of different flavors of devices or transistors. For example, besides devices for high speed and low power logic, such as core devices, high-voltage I/O transistors, i.e. EO devices, which are able to operate at higher supply voltage, have to be implemented. However, such co integration may pose a challenge due to constrained NS-NS space. A conventional method for integrating a core GAA device with a Fin EO has been designed, in which Fin EO requires extra selective stack-etch and separate selective silicon (Si) epitaxial (epi) process. Thus, the overall process is substantially costly and prone to variability issues. Another method for integrating the core GAA device with a partial GAA (pGAA) EO has also been provided. pGAA I/O are least complex to fabricate with respect to the core GAA device, thus cost effective. pGAA I/O fabrication follows the core process, i.e. NW/NS release etch followed by gate oxidation. However, since the gate control is not perfect, this method may suffer from severe short channel effect (SCE) degradation. Yet another method for integrating the core GAA device with a super lattice I/O has also been devised. The super-lattice I/O is easy to fabricate (as they are etch skipped) with respect to the core GAA device, thus cost effective. However, the super-lattice I/O exhibits several fundamental/process concerns. For example, gate oxide process optimization at each Si/SiGe interface, pFET threshold voltage mismatch between Si and SiGe regions (-100 mV), and nFET compressive stress due to SiGe-Si layers. Thus, there exists a technical problem of the conventional pGAA and FinFET I/O devices that have inadequacy in basic properties with respect to performance and stress when co-integrated with core devices.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional methods for (namely, methods of) forming the semiconductor device on a substrate.

SUMMARY

The disclosure seeks to provide an improved semiconductor device that comprises at least a first and a second Si element on a substrate. The disclosure further seeks to provide an improved method for (namely, method of) forming the semiconductor device on a substrate that comprises at least a first and a second Si element on the substrate. The disclosure provides a solution to the existing problem of the conventional GAA and FinFET I/O devices that have inadequacy in basic properties with respect to performance and stress in the co-integrated I/O devices. An objective of the disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides a semiconductor device that comprises at least a first and a second Si element on a substrate and further an improved method for (namely, method of) forming the semiconductor device that comprises at least a first and a second Si element on a substrate.

One or more objectives of the disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the disclosure are further defined in the dependent claims.

In one aspect, the disclosure provides a semiconductor device that comprises at least a first silicon (Si) element and a second Si element on a substrate, and a ferroelectric layer surrounding the first Si element and the second Si element on at least three sides and a gate-stack arranged around the ferroelectric layer.

The disclosed semiconductor device includes a ferroelectric layer surrounding the Si elements on at least three sides as the negative capacitance (NC) improves swing in pGAA I/O devices. Thus, the NC properties of the semiconductor device manifests improved performance despite the I/O device being a pGAA. Further, the disclosed semiconductor device reduces co integration challenges as the integration is done with conventional GAA flow, thus manifesting cost-effectiveness. Moreover, the single gate arranged around the ferroelectric layer in the disclosed semiconductor device allows aggressive scaling of the Fin pitch, and enhanced performance by reducing parasitic capacitance.

In an implementation form, each of the first Si element and the second Si element is surrounded by a gate insulating layer. The at least first and second Si elements include at least two Si layers stacked above each other in a direction from the substrate and each gate insulating layer is fully surrounded by the ferroelectric layer.

It is advantageous to have the ferroelectric layer surround the Si layers in the SI elements on at least three sides in order to improve the NC swing in Ferro-pGAA I/O devices. In an embodiment, the Si elements may be manifested as nanowires (NW) or nanosheets (NS) to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes. Vertical NW/NS GAA FETs may enable highly dense memory cells, such as static random-access memory (SRAMs) (with improved read and write stability). The vertical NW/NS GAA FETs may further be used as selector devices for ultra-scaled magneto resistive random access memory (MRAMs) with lower energy consumption values. Such cells may be manufactured by a cost-effective, co-integration scheme with a triple-gate FinFET or a lateral NW/NS GAA FET high-performance logic platform for increased on-chip memory content. Despite partial GAA scheme, improved performance may be observed due to NC- properties. Expected performance of such a semiconductor device, such as Ferro-pGAA device, plotted against drive current vs applied voltage is higher than other devices, such as pGAA and superlattice devices.

In a further implementation form, the at least first and second Si elements are fins, each fin contacting the substrate by one side, the other sides of the fins surrounded by the ferroelectric layer.

It is advantageous to to have the first and second Si elements as fins as the resulting FinFETs provide better SCEs, so channel doping becomes optional. This may imply that FinFETs suffer less from dopant-induced variations. Low channel doping may ensure better mobility of the carriers inside the channel, hence, higher performance. FinFETs further provide higher drive current for a given transistor footprint, hence higher speed, lower leakage, hence lower power consumption, no random dopant fluctuation, consequently better mobility and scaling of the transistor beyond 28nm.

In a further implementation form, the gate-stack is arranged to surround the ferroelectric layer in such a way that it partially surrounds each Si layer.

By virtue of such arrangement, the gate structure improves gate control by increasing gate- channel coupling, reducing off-state current, and reducing SCEs.

In a further implementation form, the semiconductor device is an input/output (I/O) device.

It is advantageous to have a Ferro-pGAA or Fe-FinFET device, as a semiconductor device, used for I/O applications, as I/O devices operate at relatively high supply voltage (2.5V ~ 1.8V) to support periphery devices. Higher supply voltage requires thick oxide thickness (~4.5nm) at larger gate length (100~250nm).

In a further implementation form, comprising one or more semiconductor devices according to any one of the preceding claims and one or more core devices, wherein the space between each semiconductor device and core device is filled with ferroelectric material.

It is advantageous to fill all the space between each semiconductor device and core device with a ferroelectric material during oxide formation process. The ferroelectric material may be a hafnium-based oxide with a high dielectric constant (such as, a k-value higher than about 3.9) and ferroelectric behavior. The ferroelectric material reduces the subthreshold voltage swing of the semiconductor devices below the threshold of the 60 mV/decade. As a result, a FeFET requires lower operating voltage to produce the same current density as a MOSFET and uses less power — which results in improved battery life, lower energy costs, and less heat generation. Further, a FeFET exhibits lower off-current compared to a MOSFET due to its steeper subthreshold voltage swing (e.g., <60 mV/decade).

In another aspect, the disclosure provides a method for (namely, method of) forming a semiconductor device on a substrate. The method includes providing a first stack of alternating layers of SiGe and Si on a substrate including at least two Si layers, the first stack intended to form the semiconductor device, removing the SiGe layers of the first stack, applying a gate insulating layer around each Si layer of the first stack, applying a ferroelectric layer around each gate insulating layer in such a way that twoor more ferroelectric layers are in physical contact with each other, and forming a gate-stack around the ferroelectric layers.

The disclosed method proposes that the semiconductor device is an I/O device. The method further comprising forming a core device on the same substrate comprising providing a second stack of alternating layers of SiGe and Si on the substrate, the second stack intended to form a core device. The method comprising the following steps before applying the ferroelectric layer around the gate insulating layers in the first stack: removing the SiGe layers on the second stack, applying a gate insulating layer around each Si layer in the second stack, applying a mask on the first stack, forming a gate-stack on the second stack, applying a mask on the second stack, and removing the mask on the first stack.

The disclosed method proposes the steps before removing the SiGe layers of forming dummy gates around the first and the second stack, forming spacers and S/D epi on the first and the second stack, and removing the dummy gates from the first and the second stack. The method further comprises the step of contact formation to the I/O device in a conventional manner.

It is to be appreciated that all the aforementioned implementation forms can be combined in various ways.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the disclosure are susceptible to being combined in various combinations without departing from the scope of the disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is an illustration of a side view of a semiconductor component comprising one or more semiconductor devices, such as a semiconductor device and one or more core devices, such as a core device, in accordance with an embodiment of the disclosure;

FIG. 2 is an illustration of a side view of a semiconductor device that includes a substrate and an FET formed on the substrate, in accordance with an embodiment of the disclosure; FIG. 3 is an illustration of a side view of a semiconductor component comprising one or more semiconductor devices, such as a semiconductor device and one or more core devices, such as a core device, in accordance with an embodiment of the disclosure;

FIG. 4 is an illustration of a side view of a semiconductor device that includes fins and sub-fins, a dielectric barrier, and an FET formed on the substrate, in accordance with an embodiment of the disclosure;

FIG. 5 is an illustration of a side view of a semiconductor device that includes fins and sub-fins, and an FET formed on the substrate, in accordance with an embodiment of the disclosure;

FIGs. 6A-6I collectively represent a method for (namely, method of) forming a semiconductor component, in accordance with an embodiment of the disclosure;

FIG. 7A is a flowchart of a method for (namely, method of) forming a semiconductor device on a substrate, in accordance with an embodiment of the disclosure; and

FIG. 7B is a flowchart of a method for (namely, method of) forming a core device on same substrate, in accordance with an embodiment of the disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non- underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the disclosure and ways in which they can be implemented. Although some modes of carrying out the disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the disclosure are also possible.

In FIG. 1, there is shown a side view illustration of a semiconductor component 100 comprising one or more semiconductor devices, such as a semiconductor device 102 and one or more core devices, such as a core device 122 in accordance with an embodiment of the disclosure. With reference to FIG. 1, there is shown a side view of the semiconductor device 102 that includes a substrate 104 and a field effect transistor (FET) 106 formed on the substrate 104 The semiconductor device 102 includes a first silicon (Si) element 108A and a second Si element 108B. The semiconductor device 102 further includes a first gate insulating layer 110A and a second gate insulating layer HOB surrounding the first Si element 108A and the second Si element 108B, respectively. The semiconductor device 102 further includes a ferroelectric layer 112 surrounding the first gate insulating layer 110A and a second gate insulating layer HOB on all the four sides. The semiconductor device 102 further includes a gate-stack 114 arranged around the ferroelectric layer 112. The substrate 104 of the semiconductor device 102 is isolated from other substrates on either sides by an isolation material, such as thermal grown oxide 116.

As illustrated in FIG. 1, in accordance with an embodiment, the first Si element 108 A and the second Si element 108B include two Si layers stacked above each other in the direction from the substrate 104 and fully surrounded by the ferroelectric layer 112. The first Si element 108A and the second Si element 108B, surrounded by the first gate insulating layer 110A and the second gate insulating layer HOB respectively, is further surrounded collectively by the ferroelectric layer 112 to form a first arrangement, contacting the substrate 104 by one side. By other three sides, the gate-stack 114 is arranged to surround the ferroelectric layer 112 in such a way that each Si layer is partially surrounded by the gate-stack 114.

In accordance with an embodiment of the present disclosure, as illustrated in FIG. 1, the semiconductor device 102 may include a third gate insulating layer HOC that is configured to isolate the two Si layers stacked above each other in the FET 106 from the substrate 104. The third gate insulating layer HOC is configured to electrically isolate the one or more layers or nanosheets of the two Si layers stacked close to the substrate 104 from the substrate 104.

The substrate 104, also be referred as a single wafer or a chip, is made up of a semiconductor material such as, silicon (Si) or germanium (Ge) and the like. In an embodiment, in the semiconductor material of the substrate 104, a p-type dopant may be added. Therefore, the substrate 104 may also be referred as a p-type semiconductor. Generally, a p-type semiconductor is one in which majority charge carriers are holes. Examples of the p-type dopants are, but not limited to, Boron (B), Indium (In), and the like. The substrate 104 may also have an isolation property. In another embodiment, the substrate 104 may have an n-type doping hence, may be referred as a n-type semiconductor. Generally, an n-type semiconductor is one in which majority charge carriers are electrons. Examples of the n-type semiconductor are, but not limited to, Phosphorus (P), Arsenic (As), Antimony (Sb), and the like. The FET 106 is a transistor which uses an electric field to control a flow of current. The FET 106 is configured to control the flow of current by applying a voltage signal to the gate-stack 114 that results into conductivity beween a source region and a drain region (not shown) of the FET 106. In a case, when the substrate 104 is the p-type semiconductor, the FET 106 that is formed on the substrate 104 is an n-type FET (or N-FET). In another case, when the substrate 104 is of the n-type semiconductor, the FET 106 will be a p-type FET (or P-FET).

In accordance with an embodiment, as illustrated in FIG. 1, the FET 106 of the semiconductor device 102 and the FET 126 of the core device 122 are fabricated as gate-all-around (GAA) structures. Thus, the FET 106 of the semiconductor device 102 may be also referred to as FeFET pGAA NS, pFe-GAA, FE-FET EO device, and Ferro pGAA EO device, without deviating from the scope of the disclosure. On the other hand, the FET 126 of the core device 122 may be also referred to as core GAA or core device GAA.

Corresponding to various devices, such as the semiconductor device 102 and the core device 122, the semiconductor component 100 includes various regions of a substrate having one or more field-effect transistors (FETs) formed thereon. For example, corresponding to the semiconductor device 102, a region of the substrate, such as the substrate 104, has the FET 106 formed thereon. Further, corresponding to the core device 122, another region of the substrate, such as the substrate 124, has the FET 126 formed thereon. Although not shown for the sake of simplicity, the FET 106 also includes a source region and a drain region that flank the vertical stack such that the first arrangement is configured to provide a conduction path between the source region and the drain region depending on a voltage signal applied to the gate-stack 114. The source region and the drain region of the FET 106 form the sides (e.g. a left side and a right side) of the vertical stack. The source region and the drain region may be formed by n-type doping into the Silicon (Si) or Germanium (Ge) or Silion-Germanium (SiGe) semiconductor material. Therefore, the source region and the drain region may also be referred as n-type semiconductor. The source region and the drain region may be one or more in the FET 106 that may be epitaxially formed on the substrate 104. In the semiconductor device 102, the third gate insulating layer HOC performs electrical isolation in order to maintain a channel stress (or a stress between the source region and the drain region) that further maintains the performance (or the performance-power trade off design) of the semiconductor device 102. In this way, the semiconductor device 102 manifests one stack of nanosheets to provide the electrical conduction between the source region and the drain region. The first Si element 108A and the second Si element 108B may correspond to silicon elements that form channels in the gate-stack 114 to provide the electrical conduction between the source region and the drain region of the semiconductor device 102. In accordance with an embodiment, as illustrated in FIG. 1, the first Si element 108A and the second Si element 108B are manifested by nanosheets that form a vertical stack in the direction from the substrate 104. Nanosheets boost current or narrow to limit power consumption and facilitates scaling and performance of the semiconductor device 102. Broadly, sacrificial layers, selective chemical etchants, and advanced atomically precise deposition technology are needed to make nanosheets. Such an FET 106 having nanosheets, as the first Si element 108A and the second Si element 108B, may be referred to as a FeFET pGAA NS or pGAA FET NS.

The first gate insulating layer 110A and the second gate insulating layer HOB may correspond to gate dielectric layers over the channels manifested by the first Si element 108A and the second Si element 108B respectively in the FET 106. The gate dielectric layer may include an interfacial layer (IL) deposited, by one of various appropriate methods, such as, atomic layer deposition (ALD), chemical vapor deposition (CVD) and ozone oxidation. The IL may include oxide, oxynitride, and HfSiO. The gate dielectric layer may also include a high-k (HK) dielectric layer deposited on the IL by suitable techniques, such as ALD, CVD, metalorganic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, or other suitable techniques. The HK dielectric layer may include LaO, Ta205, Y203, SrTi03 (STO), BaTi03 (BTO), AIO, ZrO, TiO, BaZrO, HfZrO, HfTaO, HfSiO, (Ba,Sr)Ti03 (BST), A1203, Si3N4, HfLaO, HfSiO, LaSiO, AlSiO, oxynitrides (SiON), or other such materials.

The third gate insulating layer HOC may also correspond to a gate dielectric layer that acts as a buried oxide layer between the substrate 104 and the FET 106 formed on the substrate 104 of the semiconductor device 102. The third gate insulating layer HOC reduces the parasitic junction capacitance of the semiconductor device 102. The reduced parasitic capacitance may lead to lower delay, dynamic power consumption, and thus higher performance of the semiconductor device 102. The third gate insulating layer HOC mitigates unwanted leakage paths which are far from the gate-stack 114, thereby leading to lower power consumption.

The ferroelectric layer 112 is a ferroelectric material sandwiched between the gate-stack 114 and source-drain conduction regions, i.e. the channels formed by the first Si element 108A and the second Si element 108B, of the semiconductor device 102. A property of the ferroelectric layer 112, referred to as permanent electrical field polarisation, causes the semiconductor device 102 to retain its state (on or off) in the absence of any electrical bias. Therefore, the channel conductance is used to detect the polarization state in the ferroelectric layer 112 so that data reading operation in the semiconductor device 102 is non-destructive. The FET 106 that comprises the ferroelectric layer 112 surrounding the first gate insulating layer 110A and the second gate insulating layer HOB on all the four sides may be referred to as ferroelectric field- effect transistor (Fe-FET). Various features of such Fe-FETs may include, but are not limited to, fast switching speed in ferroelectric materials, non-destructive readout, non-volatile memory state, and simple structure for high-density integration. In accordance with an embodiment of the present disclosure, hafnium zirconium oxide (HfD.5Zr0.5O2, HZO) may be used as the ferroelectric material in the ferroelectric layer 112.

In accordance with an embodiment, negative capacitance (NC) gate insulators in the FET 106, i.e. Fe-FET, may be used to reduce subthreshold swing (SS) associated with the FET 106 below Boltzmann limit of 60 mV/decade, which in turn defines the lower limit of power dissipation. Thus, NC gate insulators in the FET 106 with HZO may achieve a steep SS without losing the drive current.

The gate-stack 114 in the FET 106 is the conductive element to which when a voltage is applied, the FET 106 is enabled to control the flow of the current, which in turn alters the conductivity between the drain and source regions. Based on one configuration, as illustrated in FIG. 1, the gate-stack 114 in the FET 106 is arranged to surround the ferroelectric layer 112 in such a way that it fully surrounds the first gate insulating layer 110A and a second gate insulating layer 110B which are further surrounding the first Si element 108A and the second Si element 108B.

The thermal grown oxide 116 is an isolation material that is used to isolate the substrate 104 of the semiconductor device 102 from other substrates, such as the substrate 124, of other devices, such as the core device 122. In accordance with an embodiment, shallow trench isolation (STI) technique may be used for sub-0.5pm technology, because it completely avoids the bird's beak shape characteristic. With its zero oxide field encroachment, the STI is a suitable technique for the increased density requirements, because it allows to form smaller isolation regions. In the STI process, a shallow trench is etched into silicon substrate, such as the substrate 124. After underetching of the oxide pad, also a thermal oxide in the trench is grown, the so-called liner oxide. The thermal oxidation process is stopped after the formation of a thin oxide layer, and the rest of the trench is filled with a deposited oxide. Excessive (deposited) oxide is removed with chemical mechanical planarization and at last, nitride mask is also removed.

With reference to the core device 122 shown in FIG. 1, there is shown a side view of a substrate 124 and an FET 126 formed on the substrate 124. The core device 122 includes a first Si element 128A and a second Si element 128B. The core device 122 further includes a first gate insulating layer 130A and a second gate insulating layer 130B surrounding the first Si element 128A and the second Si element 128B, respectively. The core device 122 further includes a gate-stack 132 surrounding the first gate insulating layer 130A and a second gate insulating layer 130B on all the four sides. The core device 122 further includes a hard mask (HM) layer 134 arranged around the gate-stack 132. The substrate 124 of the core device 122 is isolated from other substrates, such as a substrate 104, of other devices, such as the semiconductor device 102, on either sides by an isolation material, such as thermal grown oxide 136.

It may be noted that the substrate 124, the first Si element 128A, the second Si element 128B, the first gate insulating layer 130A, the second gate insulating layer 130B, the gate-stack 132 and the thermal grown oxide 136 of the core device 122 are similar to the substrate 104, the first Si element 108 A, the second Si element 108B, the first gate insulating layer 110A, the second gate insulating layer HOB, the gate-stack 114 and the thermal grown oxide 116, respectively, of the semiconductor device 102, without any deviation from the scope of the disclosure.

The HM layer 134 may be used to act as a potential etch stop for the core device 122 and protect the core device 122 from any unwanted processing (e.g. etching). In accordance with an embodiment, the HM layer 134 includes an oxide layer underlying a silicon nitride layer. In accordance with another embodiment, the HM layer 134 may consist of one or more than two layers. The HM layer 134 may be then patterned using a photolithography process, and used to form a gate-stack on the EO well of the core device 122, including oxide portion, poly portion, and hard mask. In accordance with such an embodiment, the HM layer 134 protects a portion of the poly layer disposed above the I/O well of the core device 122 so that a poly structure for of the core device 122 may next be formed, for example using an etching process. A hard mask is then formed and patterned, followed by an etching step to define the gate-stack 114 of the core device 122. In accordance with an embodiment, when the semiconductor component 100 comprises one or more semiconductor devices (that include the semiconductor device 102) co-integrated with one or more core devices (that include the core device 122) and fabricated on a single subsrate, there exist spaces between such devices. Such spaces are filled with ferroelectric material. In accordance with an embodiment, the semiconductor component 100 comprising the one or more semiconductor devices and the one or more core devices, multiple STI structures may be formed in the single substrates. The STIs thus formed in effect divide the single substrate into separate areas, or wells for the one or more semiconductor devices and the one or more core devices.

In FIG. 2, there is shown a side view illustration of a semiconductor device 202 that includes a substrate 204 and an FET 206 formed on the substrate 204 in accordance with an embodiment of the disclosure. The semiconductor device 202 includes a first Si element 208A and a second Si element 208B. The semiconductor device 202 further includes a ferroelectric layer 212 surrounding the first Si element 208A and the second Si element 208B on all the four sides. The semiconductor device 202 further includes a gate-stack 214 arranged around the ferroelectric layer 212. The substrate 204 of the semiconductor device 202 is isolated from other substrates by an isolation material, such as thermal grown oxide 216.

The semiconductor device 202 is similar to the semiconductor device 102 except that the ferroelectric layer 212 surrounds the first Si element 208A and the second Si element 208B on all the four sides without any intervening gate insulating layer. Also, unlike the semiconductor device 102, the semiconductor device 202 does not include any insulating layer to isolate the two Si layers stacked above each other in the FET 206 from the substrate 204.

As illustrated in FIG. 2, in accordance with an embodiment, the first Si element 208 A and the second Si element 208B include two Si layers stacked above each other in the direction from the substrate 204 and fully surrounded by the ferroelectric layer 212. The first Si element 208A and the second Si element 208B is surrounded collectively by the ferroelectric layer 212 to form a second arrangement, contacting the substrate 204 by one side. By other three sides, the gate- stack 214 is arranged to surround the ferroelectric layer 212 in such a way that each Si layer is partially surrounded.

In accordance with an embodiment, as illustrated in FIG. 2, the FET 206 of the semiconductor device 202 is fabricated as GAA structure. Thus, the FET 206, similar to the FET 106, of the semiconductor device 202 may be also referred to as FeFET pGAA NS, pFe-GAA, FE-FET I/O device, and Ferro pGAA I/O device, without deviating from the scope of the disclosure.

In FIG. 3, there is shown a side view illustration of a semiconductor component 300 comprising one or more semiconductor devices, such as a semiconductor device 302 and one or more core devices, such as a core device 322 in accordance with an embodiment of the disclosure. With reference to FIG. 3, there is shown a side view of the semiconductor device 302 that includes a substrate 304 and an FET 306 formed on the substrate 304. The semiconductor device 302 includes a first Si element 308A and a second Si element 308B. The semiconductor device 302 further includes a first gate insulating layer 310A and a second gate insulating layer 310B surrounding the first Si element 308A and the second Si element 308B, respectively. The semiconductor device 302 further includes a ferroelectric layer 312 surrounding the first gate insulating layer 310A and a second gate insulating layer 310B on all the four sides. The semiconductor device 302 further includes a gate-stack 314 arranged around the ferroelectric layer 312. The substrate 304 of the semiconductor device 302 is isolated from other substrates by an isolation material, such as thermal grown oxide 316.

As illustrated in FIG. 3, in accordance with an embodiment, the first Si element 308 A and the second Si element 308B include two Si layers stacked above each other in the direction from the substrate 304 and fully surrounded by the ferroelectric layer 312. The first Si element 308A and the second Si element 308B, surrounded by the first gate insulating layer 310A and the second gate insulating layer 310B respectively, is further surrounded collectively by the ferroelectric layer 312 to form a third arrangement, contacting the substrate 304 by one side. By other three sides, the gate-stack 314 is arranged to surround the ferroelectric layer 312 in such a way that each Si layer is partially surrounded by the gate-stack 314.

In accordance with an embodiment of the present disclosure, as illustrated in FIG. 3, the semiconductor device 302 may include a third gate insulating layer 310C that is configured to isolate the two Si layers stacked above each other in the FET 306 from the substrate 304. The third gate insulating layer 310C is configured to electrically isolate the one or more layers or nanowires of the two Si layers stacked close to the substrate 304 from the FET 306.

With reference to the core device 322 shown in FIG. 3, there is shown a side view of a substrate 324 and an FET 326 formed on the substrate 324. The core device 322 includes a first Si element 328A and a second Si element 328B. The core device 322 further includes a first gate insulating layer 330A and a second gate insulating layer 330B surrounding the first Si element 328A and the second Si element 328B, respectively. The core device 322 further includes a gate-stack 332 surrounding the first gate insulating layer 330A and a second gate insulating layer 330B on all the four sides. The core device 322 further includes an HM layer 334 arranged around the gate-stack 332. The substrate 324 of the core device 322 is isolated from other substrates, such as a substrate 304, of other devices, such as the semiconductor device 302, on either sides by an isolation material, such as thermal grown oxide 336.

The semiconductor device 302 is similar to the semiconductor device 102 except that the first Si element 308A and the second Si element 308B in the semiconductor device 302 are manifested by nanowires (instead of nanosheets, as shown as first Si element 108A and the second Si element 108B in the semiconductor device 102) that form a vertical stack in the direction from the substrate 304. The first Si element 308A and the second Si element 308B may correspond to silicon elements that form channels in the gate-stack 314 to provide the electrical conduction between the source region and the drain region of the semiconductor device 302. In accordance with an embodiment, as illustrated in FIG. 3, the first Si element 308A and the second Si element 308B are manifested by nanowires that form a vertical stack in the direction from the substrate 304. Nanowires are optimal for low-power requirements. The FET 306 having nanowires, as the first Si element 308A and the second Si element 308B, may be referred to as a FeFET pGAA NW or pGAA FET NW.

It may be noted that the substrate 304, the first Si element 308A, the second Si element 308B, the first gate insulating layer 310A, the second gate insulating layer 310B, the third gate insulating layer 310C, the gate-stack 314, and the thermal grown oxide 316 of the semiconductor device 302 correspond to the substrate 104, the first Si element 108A, the second Si element 108B, the first gate insulating layer 110A, the second gate insulating layer HOB, the third gate insulating layer HOC, the gate-stack 114 and the thermal grown oxide 116, of the semiconductor device 102, respectively.

Similarly, the substrate 324, the first Si element 328A, the second Si element 328B, the first gate insulating layer 330A, the second gate insulating layer 330B, the third gate insulating layer 310C, the gate-stack 332, the HM layer 334, and the thermal grown oxide 336 of the core device 322 correspond to the substrate 124, the first Si element 128A, the second Si element 128B, the first gate insulating layer 130A, the second gate insulating layer 130B, the third gate insulating layer 130C, the gate-stack 132, the HM layer 134, and the thermal grown oxide 136 of the core device 122, respectively.

In FIG. 4, there is shown a side view illustration of a semiconductor device 402 that includes a first Si element 408A and a second Si element 408B (as fins), sub-fins 404A and 404B (collectively referred to as a substrate 404), a dielectric barrier 410, and an FET 406 formed on the substrate 404, in accordance with an embodiment of the disclosure. The semiconductor device 402 includes the first Si element 408A and the second Si element 408B, interchangably referred to as the fins. The semiconductor device 402 further includes a ferroelectric layer 412 surrounding the first Si element 408A and the second Si element 408B on three sides. The semiconductor device 402 further includes a dielectric barrier 410 between the first Si element 408A and the second Si element 408B, which may be used to control thickness in large fin- pitch (FP) devices. The semiconductor device 402 further includes a gate-stack 414 arranged around the ferroelectric layer 412. The sub-fins 404A and 404B of the semiconductor device 402 are isolated from each other and other substrates by an isolation material, such as thermal grown oxide 416A, 416B, and 416C.

As illustrated in FIG. 4, in accordance with an embodiment, each fin that is the first Si element 408A and the second Si element 408B, contact the substrate 404 by one side (i.e. the bottom side). The other sides of the first Si element 408A and the second Si element 408B are surrounded by the ferroelectric layer 412. The first Si element 408A and the second Si element 408B include two Si layers arranged in parallel to each other orthogonal to the direction from the substrate 104 and partially surrounded by the ferroelectric layer 112 to form a fourth arrangement. In accordance with such embodiment, the FET 406 is formed to be a Ferro FinFET with single gate.

It may be noted that the substrate 404, the first Si element 408A, the second Si element 408B, the ferroelectric layer 412, the gate-stack 414, and the thermal grown oxide 416A, 416B, and 416C of the semiconductor device 402 correspond to the substrate 104, the first Si element 108A, the second Si element 108B, the gate-stack 114 and the thermal grown oxide 116, of the semiconductor device 102, respectively.

In FIG. 5, there is shown a side view illustration of a semiconductor device 502 that includes a first Si element 508A and a second Si element 508B (as fins), sub-fins 504A and 504B (collectively referred to as a substrate 504), and an FET 506 formed on the substrate 504, in accordance with an embodiment of the disclosure. The semiconductor device 502 includes the first Si element 508A and the second Si element 508B, interchangably referred to as the fins. The semiconductor device 502 further includes a ferroelectric layer 512 surrounding the first Si element 508A and the second Si element 508B on three sides. The semiconductor device 502 further includes a gate-stack 514 arranged around the ferroelectric layer 512. The sub-fins 504A and 504B of the semiconductor device 502 is isolated from each other and other substrates by an isolation material, such as thermal grown oxide 516A, 516B, and 516C.

The semiconductor device 502 is similar to the semiconductor device 402 except that the semiconductor device 502 does not include any dielectric barrier corresponding to the dielectric barrier 410, as shown in the semiconductor device 402. It may be noted that the substrate 504, the first Si element 508A, the second Si element 508B, the ferroelectric layer 512, the gate- stack 514, and the thermal grown oxide 516A, 516B, and 516C of the semiconductor device 502 correspond to the substrate 404, the first Si element 408A, the second Si element 408B, the ferroelectric layer 412, the gate-stack 414, and the thermal grown oxide 416A, 416B, and 416C of the semiconductor device 402.

Embodiment of the disclosure are in contradistinction to a conventional semiconductor devices, such as FinFET, Superlattice FET, and pGAAFET. For example, in a conventional FinFET, Fin EO requires extra selective stack-etch and separate selective silicon (Si) epitaxial (epi) process. Therefore, the conventional FinFET is an overall costlier process (due to extra mask and Fin- epi) and is prone to variability issues (as thermal budget leads to integration issues). In a conventional Superlattice FET, there is observed gate oxide process optimization issues, thus compromised nl _dsat at each Si/SiGe interface. Further, there exists pFET threshold voltage (pVt) mismatch between Si and SiGe regions (-100 mV), and nFET compressive stress due to SiGe- Si layers. Therefore, the conventional Superlattice FET has several fundamental/process concerns. In a conventional pGAAFET, the gate control is not perfect that manifests severe SCE degradation. Therefore, in the conventional pGAAFET, the I _dsat may be approximately 20% lower. Further, there is observed n/p SCE degradation in such pGAAFET. The semiconductor devices 102, 202, and 302 overcome the aforementioned drawbacks associated with the conventional methods, as the semiconductor devices 102, 202, and 302 exibit recovered SCE, n/p I _dsat , and cost effective integration flow. Further, the semiconductor devices 402 and 502 exhibit scaling of Fin Pitch, in addition to the recovered SCE and n/p I _dsat. FIGs. 6A-6I collectively represent a method for (namely, method of) forming a semiconductor component, in accordance with an embodiment of the disclosure. FIGs. 6A-6I are described in conjunction with elements from FIGs. 1, 2, 3, 4, and 5. With reference to FIGs. 6A-6I, there is shown a method 600 for (namely, method of) manufacturing a semiconductor component 602. The method 600 includes steps 601 to 617.

The method 600 collectively describes the steps of forming a semiconductor component 602, which is similar to one of the semiconductor components 100 or 300, except for the fact that the devices in the semiconductor component 602 include two sub-stacks of the Si elements, without any variation from the scope of the disclosure. The semiconductor component 602 comprises a semiconductor device 604, similar to one of the semiconductor devices 102, 202, 302, 402, or 502 illustrated in FIGs. 1, 2, 3, 4, and 5, respectively, except for the fact that the semiconductor device 604 includes two stacks of the Si elements.

The semiconductor component 602 further comprises a core device 606, similar to one of the core devices 122 or 322 illustrated in FIGs. 1 and 3, respectively, except for the fact that the core device 606 includes two stacks of the Si elements.

Each step of the method 600 is represented by a dashed rectangular box in each of the FIGs. 6A-6I, that is used for illustration purpose only. Additionally, each of the semiconductor device 604 and the core device 606 is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.

With reference to FIG. 6A, at step 601, a first stack of alternating layers of SiGe and Si on the substrate 104 including at least two Si layers is provided in the semiconductor device 604. The first stack comprises a first Si element 604C, a first SiGe element 604A, a second Si element 604D, and a second SiGe element 604B. The first stack is intended to form the semiconductor device 604.

Similarly, a second stack of alternating layers of SiGe and Si on the substrate 124 including at least two Si layers is provided in the core device 606. The second stack comprises a first Si element 606C, a first SiGe element 606A, a second Si element 606D, and a second SiGe element 606B. It may be noted that the substrate 104 and the substrate 124 are parts of a single substrate for the semiconductor component 602. In accordance with an embodiment, as illustrated in FIG. 6 A and FIG. 1, the first and the second stacks of nanosheet strips are formed including Si nanosheet strips and SiGe nanosheet strips stacked alternatively. In accordane with another embodiment, as illustrated in FIG. 3, the first and the second stacks of nanowire strips are formed including Si nanowire strips and SiGe nanowire strips stacked alternatively. The SiGe nanosheet/nanowire strips are used as sacrificial strips and the Si nanosheet/nanowire strips are used as the semiconductor body or channel of each of the pGAA FETs corresponding to the semiconductor device 604 and the core device 606. It may be noted that the first and second stacks comprising alternate layers of SiGe and Si on corresponding substrates are formed through epitaxial growth.

In accordance with an embodiment, a vertical stack of epitaxy layers of Si and SiGe are formed over the substrates 104 and 124 and may be stacked in an alternating sequence, i.e., each epitaxy layer of Si is immediately and vertically adjacent to a different one of the epitaxy layers of SiGe. The number of epitaxy layers of Si and SiGe may vary, without any deviation from the scope of the disclosure. It may be noted that Si and SiGe have different etching rates with respect to some etchants, i.e., having etching selectivity, such that a selective etching may be conducted to remove one of the epitaxy layers with the other one remaining.

With reference to FIG. 6B, at the step 603, sub-stacks of Si elements are formed in both the semiconductor device 604 and the core device 606. More specifically, two sub-stacks of the first stack of alternating layers of SiGe and Si are formed within an area defined by STI region formed over the substrate 104. One sub-stack of the first stack comprising alternating layers of SiGe and Si, such as the first Si element 108A, a first SiGe element 610A, the second Si element 108B, and a second SiGe element 610B, is formed within an area defined by STI regions 116A and 116B formed over the substrate 104A. Other sub-stack of the first stack comprising alternating layers of SiGe and Si, such as a third Si element 108C, a third SiGe element 610C, a fourth Si element 108D, and a fourth SiGe element 610D, is formed within an area defined by STI regions 116B and 116C formed over the substrate 104B. It may be noted that the first Si element 108A and the third Si element 108C collectively correspond to the first Si element 604C (as shown as an initial whole layer in FIG. 6A), and the second Si element 108B and the fourth Si element 108D collectively correspond to the second Si element 604D (as shown as an initial whole layer in FIG. 6A). Similarly, it may be noted that the first SiGe element 610A and the third SiGe element 610C collectively correspond to the first SiGe element 604A (as shown as an initial whole layer in FIG. 6A), and the second SiGe element 610B and the fourth SiGe element 610D collectively correspond to the second SiGe element 604B (as shown as an initial whole layer in FIG. 6A). Other correspondences between the elements of FIGs. 6A and 6B may be established in similar manner.

Similarly, two sub-stacks of the second stack of alternating layers of SiGe and Si are formed within an area defined by STI region formed over the substrate 124. One sub-stack of the second stack comprising alternating layers of SiGe and Si, such as the first Si element 128A, a first SiGe element 614A, the second Si element 128B, and a second SiGe element 614B, is formed within an area defined by STI regions 136A and 136B formed over the substrate 124A. Other sub-stack of the second stack comprising alternating layers of SiGe and Si, such as a third Si element 128C, a third SiGe element 614C, a fourth Si element 128D, and a fourth SiGe element 614D, is formed within an area defined by STI regions 136B and 136C formed over the substrate 124B.

A dummy oxide layer 608A, may be formed, surrounding the two sub-stacks of the first stack from three sides. The dummy oxide layer 608A may also be extended between the two sub stacks of the first stack in the semiconductor device 604. Similarly, a dummy oxide layer 612A, may be formed, surrounding the two sub-stacks of the second stack from three sides. The dummy oxide layer 612A may also be extended between the two sub-stacks of the second stack in the core device 606. The dummy oxide layers 608A and 612A may be silicon nitride or other suitable dielectric material. The dummy oxide layers 608A and 612A may be formed of a low- K dielectric material, such as, silicon oxynitride, silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), silicon mononitride (SiN), vacuum and other dielectrics or other suitable material. The dummy oxide layers 608A and 612A may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches.

Thereafter, a dummy gate 608B may be formed around the dummy oxide layer 608A that surrounds the first stack of the semiconductor component 602. Similarly, a dummy gate 612B may be formed around the dummy oxide layer 612A that surrounds the second stack of the core device 606. The dummy gates 608B and 612B may include a sacrificial polysilicon layer, a sacrificial cap layer, and a sacrificial liner layer, not shown for simplicity. The sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric material.

With reference to FIG. 6C, at the step 605, outer and inner spacers may be formed. The outer and inner spacers, not shown here for simplicity, are formed to separate the gate structure, source region and drain region from each other in the semiconductor component 602 and the core device 606. For example, inner spacers are formed laterally adjacent to the sacrificial strips to be removed/receded such that it is ensured that edge surfaces of the receded sacrificial strips are exposed from the inner spacers. Outer spacers may be formed adjacent to the sacrificial gate structure.

The inner spacers may be formed of a high-K dielectric material, such as, higher dielectric constant than that of outer spacers. The high-K material for the inner spacers may include one or more of silicon nitride Si3N4, silicon carbide (SiC), hafnium oxide (Hf02) or other suitable high-K dielectric material. In an embodiment, the K-value of the inner spacer material is between about three to four times of the K-value of the outer spacer material. In an example, the inner spacers also include one or more air gaps adjacent to one or more of the gate structure or the source/drain region.

The outer spacer may be formed of a low-K dielectric material, such as, silicon oxynitride (SiOxNy), silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), vacuum and other dielectrics or other suitable material. The outer spacer may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches.

Furthermore, source/drain (S/D) regions in both the semiconductor component 602 and the core device 606 may be formed through epitaxy procedures. Ohmic junctions between the S/D region and the channel region are ensured if edge surfaces of the sacrificial strips are not covered by the dielectric material of the inner spacers.

Once the spacers and S/D regions are formed, the dummy gates 608B and 612B that include sacrificial polysilicon layer, the sacrificial cap layer, and the sacrificial liner layer, are also removed from the semiconductor component 602 and the core device 606, respectively.

With reference to FIG. 6D, at the step 607, the sacrificial strips, i.e. the first SiGe element 610A, the second SiGe element 610B, the third SiGe element 610C, and the fourth SiGe element 610D of the first stack of the semiconductor device 604 are removed (or receded) based on selective etching process. Also, the first SiGe element 614A, the second SiGe element 614B, the third SiGe element 614C, and the fourth SiGe element 614D of the second stack of the core device 606 are removed (or receded) based on selective etching process. With reference to FIG. 6E, at the step 609, the first gate insulating layer 110A, the second gate insulating layer HOB, the fourth gate insulating layer HOD, and the fifth gate insulating layer 110E are applied around the first Si element 108A, the second Si element 108B, the third Si element 108C, and the fourth Si element 108D, respectively, in the first stack of the semiconductor device 604. The third gate insulating layer HOC is deposited on the substrate 104A and the sixth gate insulating layer 110F is deposited on the substrate 104B. Similarly, the first gate insulating layer 130A, the second gate insulating layer 130B, the fourth gate insulating layer 130D, the fifth gate insulating layer 130E are applied around the first Si element 128A, the second Si element 128B, the third Si element 128C, and the fourth Si element 128D, respectively, in the second stack of the core device 606. The third gate insulating layer 130C is deposited on the substrate 124A and the sixth gate insulating layer 130F is deposited on the substrate 124B. The gate insulating layers may be a single layer of a dielectric material, two separately formed layers of a same dielectric material or two layers of different dielectric materials.

With reference to FIG. 6F, at the step 611, a first HM 616 is deposited on the first stack of the semiconductor device 604. The first HM 616 is then patterned, and then etched to define the gate-stack of the semiconductor device 604.

With reference to FIG. 6G, at the step 613, a gate-stack 618 is formed on the second stack of the core device 606. The gate-stack 618 may include gate electrode and gate dielectric, not shown for simplicity. The gate electrode includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials. In some examples, the gate electrode may include a work function layer tuned to have a proper work function for enhanced performance of the core device 606. For example, suitable N-type work function metals include Ta, TiAl, TiAIN, TaCN, other N-type work function metal, or a combination thereof, and suitable P-type work function metal materials include TiN, TaN, other P-type work function metal, or combination thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer or a tungsten layer is formed over the work function layer such that the gate electrode includes a work function layer disposed over the gate dielectric and a conductive layer disposed over the work function layer and below a gate cap, not shown for simplicity. In an example, the gate electrode may have a thickness ranging from about 5 nm to about 40 nm, based on design requirements.

With reference to FIG. 6H, at the step 615, a second HM 620 is applied on the second stack of the core device 606, and the first HM 616 is removed from the first stack of the semiconductor device 604. Like the first HM 616, the second HM 620 may be deposited, patterned, and etched to define the gate-stack of the core device 606.

With reference to FIG. 61, at the step 617, a ferroelectric layer 622A is applied around the first gate insulating layer 110A and the second gate insulating layer 110B of the semiconductor device 604 in such a way that corresponding ferroelectric layers are in physical contact with each other. The applied ferroelectric layer 622A is also adjacent to the third gate insulating layer HOC, that is deposited on the substrate 104A. Further, another ferroelectric layer 622B is applied around the fourth gate insulating layer 110D and the fifth gate insulating layer HOE of the semiconductor device 604 in such a way that the corresponding ferroelectric layers are in physical contact with each other. The applied ferroelectric layer 622B is also adjacent to the sixth gate insulating layer HOF, that is deposited on the substrate 104B. As the ferroelectric layers 622A and 622B merge for the two sub-stacks in the first stack for the semiconductor device 604, the semiconductor device 604 is manifested into a partial GAA device. Around the ferroelectric layers 622A and 622B, a gate-stack 624 is arranged.

The gate-stack 624 may include gate electrode and gate dielectric, not shown for simplicity. The gate electrode includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials. In some examples, the gate electrode may include a work function layer tuned to have a proper work function for enhanced performance of the semiconductor device 604. For example, suitable N- type work function metals include Ta, TiAl, TiAIN, TaCN, other N-type work function metal, or a combination thereof, and suitable P-type work function metal materials include TiN, TaN, other P-type work function metal, or combination thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer or a tungsten layer is formed over the work function layer such that the gate electrode includes a work function layer disposed over the gate dielectric and a conductive layer disposed over the work function layer and below a gate cap, not shown for simplicity. In an example, the gate electrode may have a thickness ranging from about 5 nm to about 40 nm, based on design requirements.

Thereafter, conventional flow for contact information is followed. For example, middle-of-line (MOL) processes include gate contact and/or source/drain contact formation. Back-end-of-line (BEOL) processes include all wafer fabrication processes subsequent to the MOL, for example, forming the wirings in metallization layers to interconnect the individual devices.

In this way, the method 600 provides an easy process for forming a semiconductor component, such as the semiconductor component 602.

FIG. 7A is a flowchart of a method for (namely, method of) forming a semiconductor device on a substrate, in accordance with an embodiment of the disclosure. FIG. 7A is described in conjunction with elements from FIGs. 6A-6I. With reference to FIG. 7A, there is shown a method 700A for forming a semiconductor device on a substrate. The method 700A is executed to form the semiconductor device 604. It may be noted that the semiconductor device 604 is similar to the semiconductor devices 102, 202, 302, 402, and 502 illustrated in FIGs. 1, 2, 3, 4, and 5, respectively. The method 700A includes steps 702, 704, 706, 708, and 710.

The disclosure provides the method 700A for forming a semiconductor device on a substrate, wherein the method 700A includes providing a first stack of alternating layers of SiGe and Si on a substrate including at least two Si layers, the first stack intended to form the semiconductor device, removing the SiGe layers of the first stack, applying a gate insulating layer around each Si layer of the first stack, applying a ferroelectric layer around each gate insulating layer in such a way that the ferroelectric layers are in physical contact with each other, and forming a gate- stack around the ferroelectric layers.

The method 700A is disclosed for forming a semiconductor device on a substrate. The method 700A is used for forming the semiconductor device 604 on the substrates 104A and 104B (which are part of same substrate).

At the step 702, the method 700A includes providing a first stack of alternating layers of SiGe and Si on a substrate including at least two Si layers, the first stack intended to form the semiconductor device. For example, one sub-stack of the first stack comprising alternating layers of SiGe and Si, such as the first Si element 108A, a first SiGe element 610A, the second Si element 108B, and a second SiGe element 610B, is formed within an area defined by STI regions 116A and 116B formed over the substrate 104A. Other sub-stack of the first stack comprising alternating layers of SiGe and Si, such as a third Si element 108C, a third SiGe element 610C, a fourth Si element 108D, and a fourth SiGe element 610D, is formed within an area defined by STI regions 116B and 116C formed over the substrate 104B.

At the step 704, the method 700A includes removing the SiGe layers of the first stack. For example, the first SiGe element 610A, the second SiGe element 610B, the third SiGe element 610C, and the fourth SiGe element 610D of the first stack of the semiconductor device 604 are removed (or receded) based on selective etching process.

At the step 706, the method 700A includes applying a gate insulating layer around each Si layer of the first stack. For example, the first gate insulating layer 110A, the second gate insulating layer HOB, the fourth gate insulating layer HOD, and the fifth gate insulating layer 110E are applied around the first Si element 108A, the second Si element 108B, the third Si element 108C, and the fourth Si element 108D, respectively, in the first stack of the semiconductor device 604. The third gate insulating layer HOC is deposited on the substrate 104A and the sixth gate insulating layer 110F is deposited on the substrate 104B.

At the step 708, the method 700A includes applying a ferroelectric layer around each gate insulating layer in such a way that two or more ferroelectric layers are in physical contact with each other. For example, the ferroelectric layer 622A is applied around the first gate insulating layer 110A and the second gate insulating layer 110B of the semiconductor device 604 in such a way that corresponding ferroelectric layers are in physical contact with each other. The applied ferroelectric layer 622A is also adjacent to the third gate insulating layer HOC, that is deposited on the substrate 104A. Further, another ferroelectric layer 622B is applied around the fourth gate insulating layer HOD and the fifth gate insulating layer HOE of the semiconductor device 604 in such a way that the corresponding ferroelectric layers are in physical contact with each other. The applied ferroelectric layer 622B is also adjacent to the sixth gate insulating layer HOF, that is deposited on the substrate 104B. It may be noted that in addition to receiving control from step 706 in FIG. 7A, step 708 also receives control from step 740 in FIG. 7B. Therefore, the ferroelectric layers 622A and 622B are applied only on the first stack of the semiconductor device 604 and not on the second stack of the core device 606, as the first stack is unmasked (at step 740 in FIG. 7B) and the second stack is masked (at step 738 in FIG. 7B). As the ferroelectric layers 622A and 622B merge for the two sub-stacks in the first stack for the semiconductor device 604, the semiconductor device 604 is manifested into a partial GAA device.

At the step 710, the method 700A includes forming a gate-stack around the ferroelectric layers. For example, around the ferroelectric layers 622A and 622B, a gate-stack 624 is arranged. The gate-stack 624 may include gate electrode and gate dielectric, not shown for simplicity. The gate electrode includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials. In some examples, the gate electrode may include a work function layer tuned to have a proper work function for enhanced performance of the semiconductor device 604.

Thus, the method 700A achieves all the advantages and effects of the semiconductor device

604

The steps 702, 704, 706, 708, and 710 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

FIG. 7B is a flowchart of a method for (namely, method of) forming a core device on same substrate, in accordance with an embodiment of the disclosure. FIG. 7B is described in conjunction with elements from FIGs. 6A-6I. With reference to FIG. 7B, there is shown a method 700B for forming a core device on the same substrate. The method 700B is executed to form the core device 606. The method 700B includes steps 722, 724, 726, 728, 730, 732, 734, 736, 738, and 740.

The disclosure provides the method 700B for forming a core device on a substrate, wherein the method 700B includes providing a second stack of alternating layers of SiGe and Si on the substrate, the second stack intended to form a core device, the method 700B comprising the following steps before applying the ferroelectric layer around the gate insulating layers in the first stack removing the SiGe layers on both the first and the second stack, applying a gate insulating layer around each Si layer in both the first and the second stack, applying a mask on the first stack, forming a gate on the second stack, applying a mask on the second stack, and removing the mask on the first stack. The method 700B further comprising the steps before removing the SiGe layers of forming a dummy gate around the second stack, forming spacers and S/ epi on the second stack, and removing the dummy gate.

The method 700B is disclosed for forming a core device on the same substrate. The method 700B is used for forming the core device 606 on the substrate 124. It may be noted that the substrate 124 on which the core device 606 is formed and the substrates 10 4on which the semiconductor device 604 is formed, are different regions of the same substrate. Thus the semiconductor device 604 and the core device 606 are co-integrated on a single substrate.

At the step 722, the method 700B includes providing a second stack of alternating layers two sub-stacks of the second stack of alternating layers of SiGe and Si are formed within an area defined by STI region formed over the substrate 124. For example, one sub-stack of the second stack comprising alternating layers of SiGe and Si, such as the first Si element 128A, the first SiGe element 614A, the second Si element 128B, and the second SiGe element 614B, is formed within an area defined by STI regions 136A and 136B formed over the substrate 124A. Other sub-stack of the second stack comprising alternating layers of SiGe and Si, such as the third Si element 128C, the third SiGe element 614C, the fourth Si element 128D, and the fourth SiGe element 614D, is formed within an area defined by STI regions 136B and 136C formed over the substrate 124B.

At the step 724, the method 700B includes forming a dummy gate around the first and the second stack. For example, the dummy gate 608B may be formed around the dummy oxide layer 608A that surrounds the first stack of the semiconductor device 604. Further, the dummy gate 612B may be formed around the dummy oxide layer 612A that surrounds the second stack of the core device 606. The dummy gates 608B and 612B may include a sacrificial polysilicon layer, a sacrificial cap layer, and a sacrificial liner layer, not shown for simplicity. The sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric material.

At the step 726, the method 700B includes forming spacers and S/D epi on the first and the second stack. For example, outer and inner spacers, not shown here for simplicity, are formed to separate the gate structure, source region and drain region from each other in the semiconductor device 604 and the core device 606. For example, inner spacers are formed laterally adjacent to the sacrificial strips to be removed/receded such that it is ensured that edge surfaces of the receded sacrificial strips are exposed from the inner spacers. Outer spacers may be formed adjacent to the sacrificial gate structure, i.e. the dummy gates 608B and 612B. Further, S/D regions in the semiconductor device 604 and the core device 606 may be formed through epitaxy procedures. Ohmic junctions between the S/D region and the channel region are ensured if edge surfaces of the sacrificial strips are not covered by the dielectric material of the inner spacers.

At the step 728, the method 700B includes removing the dummy gates from the first and the second stack. For example, the dummy gates 608B and 612B that include sacrificial polysilicon layer, the sacrificial cap layer, and the sacrificial liner layer, are removed from the semiconductor device 604 and the core device 606, respectively.

At the step 730, the method 700B includes removing the SiGe layers on the second stack. For example, the first SiGe element 614A, the second SiGe element 614B, the third SiGe element 614C, and the fourth SiGe element 614D of the second stack of the core device 606 are removed (or receded) based on selective etching process. It may be noted that step 730 in FIG. 7B is executed in parallel to step 704 in FIG. 7A.

At the step 732, the method 700B includes applying a gate insulating layer around each Si layer in the second stack. For example, the first gate insulating layer 130A, the second gate insulating layer 130B, the fourth gate insulating layer 130D, the fifth gate insulating layer 130E are applied around the first Si element 128A, the second Si element 128B, the third Si element 128C, and the fourth Si element 128D, respectively, in the second stack of the core device 606. The sixth gate insulating layer 130F is deposited on the substrate 124B for isolation. The gate insulating layers may be a single layer of a dielectric material, two separately formed layers of a same dielectric material or two layers of different dielectric materials. It may be noted that step 732 in FIG. 7B is executed in parallel to step 706 in FIG. 7A.

At the step 734, the method 700B includes applying a mask on the first stack. For example, the first HM 616 is deposited on the first stack of the semiconductor device 604. The first HM 616 is then patterned, and then etched to define the gate-stack of the semiconductor device 604.

At the step 736, the method 700B includes forming a gate-stack on the second stack. For example, the gate-stack 618 is formed on the second stack of the core device 606. The gate- stack 618 may include gate electrode and gate dielectric, not shown for simplicity. The gate electrode includes a conductive material, e.g., a metal or a metal compound. At the step 738, the method 700B includes applying a mask on the second stack. For example, the second HM 620 is applied on the gate-stack 618 which is formed on the second stack of the core device 606.

At the step 740, the method 700B includes removing the mask on the first stack. For example, the first HM 616 is removed from the first stack of the semiconductor device 604. Control moves to step 708 in the method 700A of FIG. 7A.

Thus, the method 700B achieves all the advantages and effects of the core device 606.

The steps 722 to 740 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

Modifications to embodiments of the disclosure described in the foregoing are possible without departing from the scope of the disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.