Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2001/065605
Kind Code:
A1
Abstract:
A method is provided for packaging a plurality of semiconductor chips in a single resin mold so that it may be easy to test the individual semiconductor chips. The method may apply to various MCPs and system LSIs. One signal output terminal of a first semiconductor chip in a single package is internally connected with a first external terminal of a semiconductor device. One signal input terminal of a second semiconductor chip is internally connected with a second external terminal of the semiconductor device. The connection between the signal output terminal and the signal input terminal is completed by connecting the first and second external terminals of the semiconductor device outside the semiconductor device.
Inventors:
NISHIZAWA HIROTAKA (JP)
MASUDA MASACHIKA (JP)
KANEMOTO KOICHI (JP)
WADA TAMAKI (JP)
MASUDA MASACHIKA (JP)
KANEMOTO KOICHI (JP)
WADA TAMAKI (JP)
Application Number:
PCT/JP2001/001576
Publication Date:
September 07, 2001
Filing Date:
March 01, 2001
Export Citation:
Assignee:
HITACHI LTD (JP)
HITACHI ULSI SYS CO LTD (JP)
NISHIZAWA HIROTAKA (JP)
MASUDA MASACHIKA (JP)
KANEMOTO KOICHI (JP)
WADA TAMAKI (JP)
HITACHI ULSI SYS CO LTD (JP)
NISHIZAWA HIROTAKA (JP)
MASUDA MASACHIKA (JP)
KANEMOTO KOICHI (JP)
WADA TAMAKI (JP)
International Classes:
H01L25/16; G11C29/02; H01L23/495; H01L23/50; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L25/04
Foreign References:
| JPH08316407A | 1996-11-29 | |||
| JPH0513662A | 1993-01-22 | |||
| JPH09508496A | 1997-08-26 | |||
| JPH06250799A | 1994-09-09 | |||
| JPH11354714A | 1999-12-24 |
Attorney, Agent or Firm:
Asamura, Kiyoshi (New Ohtemachi Bldg. 2-1 Ohtemachi 2-chome Chiyoda-ku, Tokyo, JP)
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