Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2005/078797
Kind Code:
A1
Abstract:
First and second semiconductor chips (100, 200) are stacked and interconnected through small bumps. Therefore, circuit blocks in the first semiconductor chip is connected through the small bumps to a circuit block in the second semiconductor chip. The circuit block in the second semiconductor chip is connected to external electrodes through the first semiconductor chip by small bump connection. The small bump (121, 221) for interconnecting circuit blocks (111 to 114, 210) of the semiconductor chips (100, 200) are provided at positions different from those of the small bumps (122, 222) for connecting the circuit block (210) in the second semiconductor chip (200) to external electrodes.
Inventors:
KONDO KAZUHIRO (JP)
Application Number:
PCT/JP2005/002196
Publication Date:
August 25, 2005
Filing Date:
February 08, 2005
Export Citation:
Assignee:
SONY CORP (JP)
KONDO KAZUHIRO (JP)
KONDO KAZUHIRO (JP)
International Classes:
H01L25/18; H01L25/065; H01L25/07; (IPC1-7): H01L25/065; H01L25/07; H01L25/18
Foreign References:
| JPH05109977A | 1993-04-30 | |||
| JPH11168185A | 1999-06-22 | |||
| JPH10200062A | 1998-07-31 | |||
| JP2001156249A | 2001-06-08 |
Other References:
See also references of EP 1610383A4
Attorney, Agent or Firm:
Tsunoda, Yoshisue (8-1 Nishishinjuku 1-chom, Shinjuku-ku Tokyo, JP)
Download PDF:
Previous Patent: NON-PLANAR INTEGRATED CIRCUIT SYSTEM
Next Patent: CIRCUIT ARRANGEMENT AND METHOD FOR PROTECTING AN INTEGRATED SEMICONDUCTOR CIRCUIT
Next Patent: CIRCUIT ARRANGEMENT AND METHOD FOR PROTECTING AN INTEGRATED SEMICONDUCTOR CIRCUIT