Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2007/057972
Kind Code:
A1
Abstract:
This invention provides a semiconductor device comprising a memory cell array
and a semiconductor integrated circuit which are provided together on an identical
semiconductor substrate (1). The memory cell array is provided in a memory cell
region (mmry) and comprises a plurality of memory devices (R), provided in a matrix
form, each comprising a chalcogenide material storage layer (22) for storing
a high electric resistance state and a low electric resistance state by taking
advantage of a change in atomic arrangement. The semiconductor integrated circuit
is provided in a logic circuit region (lgc). The chalcogenide material storage
layer (22) is formed of a chalcogenide material comprising not less than 7 atomic%
and not more than 40 atomic% of at least one of Ga and In, not less than 5 atomic% and
not more than 35 atomic% of Ge, not less than 5 atomic% and not more than 25 atomic%
of Sb, and not less than 40 atomic% and not more than 65 atomic% of Te.
Inventors:
MORIKAWA TAKAHIRO (JP)
TERAO MOTOYASU (JP)
TAKAURA NORIKATSU (JP)
KUROTSUCHI KENZO (JP)
TERAO MOTOYASU (JP)
TAKAURA NORIKATSU (JP)
KUROTSUCHI KENZO (JP)
Application Number:
PCT/JP2005/021360
Publication Date:
May 24, 2007
Filing Date:
November 21, 2005
Export Citation:
Assignee:
RENESAS TECH CORP (JP)
MORIKAWA TAKAHIRO (JP)
TERAO MOTOYASU (JP)
TAKAURA NORIKATSU (JP)
KUROTSUCHI KENZO (JP)
MORIKAWA TAKAHIRO (JP)
TERAO MOTOYASU (JP)
TAKAURA NORIKATSU (JP)
KUROTSUCHI KENZO (JP)
International Classes:
H01L27/105; H01L45/00
Foreign References:
| JP2005117002A | 2005-04-28 | |||
| JP2003298013A | 2003-10-17 |
Attorney, Agent or Firm:
TSUTSUI, Yamato (6th Floor Kokusai Chusei Kaikan, 14, Gobanch, Chiyoda-ku Tokyo, JP)
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