Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2010/134267
Kind Code:
A1
Abstract:
Disclosed is a semiconductor device having a multilayer wiring structure, which has a structure that enables efficient heat dissipation from a wiring layer in the middle section. The semiconductor device comprises a lower layer-side wiring line (13), an intermediate wiring line (23), an upper layer-side wiring line (33), a first contact via (15) that is formed for the purpose of electrically connecting the lower layer-side wiring line (13) and the intermediate wiring line (23), and a second contact via (25) that is formed for the purpose of electrically connecting the intermediate wiring line (23) and the upper layer-side wiring line (33). The first and second contact vias (15, 25) respectively have a rectangular shape that has long sides extending in the same direction, and have an overlapping portion when viewed in plan.
Inventors:
ITOH KAZUO
Application Number:
PCT/JP2010/002935
Publication Date:
November 25, 2010
Filing Date:
April 22, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
ITOH KAZUO
ITOH KAZUO
International Classes:
H01L21/768; H01L21/82
Foreign References:
| JP2001156168A | 2001-06-08 | |||
| JPH07231172A | 1995-08-29 | |||
| JPH04162652A | 1992-06-08 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims: