Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/023211
Kind Code:
A1
Abstract:
Provided is a semiconductor device incorporating a test device with which variations produced in each element of a test circuit can be compensated and with which the same tests can be implemented for any semiconductor device. A data signal that alternates between 0 and 1 from a driver of an output circuit of the semiconductor device which is calibrated beforehand is input to an input circuit of the same semiconductor device. The voltage amplitude of the input signal is measured by branching the input to the input circuit. This is compared with the output amplitude of the driver and an error is stored in memory as a correction value. Also, the phase and jitter amount are measured using a clock having a prescribed phase and jitter amount. These are compared with the prescribed phase and jitter amount and errors are stored in the memory as correction values. In a test, the amplitude and jitter amount of the input signal from another IC are measured and corrected by using the correction values stored in the memory. It is therefore possible to determine whether the amplitude and jitter amount satisfy standard values.
Inventors:
YAGOSHI TERUAKI (JP)
Application Number:
PCT/JP2010/064117
Publication Date:
February 23, 2012
Filing Date:
August 20, 2010
Export Citation:
Assignee:
FUJITSU LTD (JP)
YAGOSHI TERUAKI (JP)
YAGOSHI TERUAKI (JP)
International Classes:
G01R31/28; G01R31/30
Foreign References:
| JP2004085236A | 2004-03-18 | |||
| JP2001235517A | 2001-08-31 | |||
| JP2002174664A | 2002-06-21 | |||
| JP2000338193A | 2000-12-08 |
Attorney, Agent or Firm:
OSUGA, Yoshiyuki (JP)
Yoshiyuki Osuge (JP)
Yoshiyuki Osuge (JP)
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Claims:
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