Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/073609
Kind Code:
A1
Abstract:
Multiple gate trenches (13a, 13b) are formed on the surface of an n-type drift region (11). On the inner wall of each of the gate trenches (13a, 13b), a gate electrode (15) is formed through a gate oxide film (14). A p-type base region (12a, 12b) is formed selectively between adjacent two of the gate trenches (13a, 13b) in such a manner that the p-type base region (12a, 12b) is located adjacent to the gate trenches along the length direction of the gate trenches. An n-type emitter region (16a) that is in contact with the gate trench (13a) is formed on a surface layer of the p-type base region (12a, 12b). A p-type contact region (17) which has a higher concentration than that in the p-type base region (12a) is formed on the surface layer of the p-type base region (12a) in such a manner that the p-type contact region (17) is in contact with the gate trench (13b) side of the n-type emitter region (16a). The end part of the gate trench (13b) side of the n-type emitter region (16a) is ended with the inside of the p-type contact region (17).
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Inventors:
YOSHIKAWA KOH (JP)
Application Number:
PCT/JP2011/074081
Publication Date:
June 07, 2012
Filing Date:
October 19, 2011
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
YOSHIKAWA KOH (JP)
YOSHIKAWA KOH (JP)
International Classes:
H01L29/739; H01L21/336; H01L29/78
Foreign References:
| JP2007221012A | 2007-08-30 | |||
| JPS61156882A | 1986-07-16 | |||
| JP2000228519A | 2000-08-15 | |||
| JP2001274400A | 2001-10-05 | |||
| JP2008311301A | 2008-12-25 | |||
| JP2008135522A | 2008-06-12 | |||
| JP2010034285A | 2010-02-12 | |||
| JP2003197912A | 2003-07-11 | |||
| JP2006210547A | 2006-08-10 |
Attorney, Agent or Firm:
SAKAI, AKINORI (JP)
Akinori Sakai (JP)
Akinori Sakai (JP)
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Claims: