SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2015/177910

A1

In a mesa section between trenches (2), a planar MOSFET (5) is provided on the upper surface of an N- type semiconductor substrate (1). In the mesa section, a P+ type emitter layer (6) is provided between the trench (2) and the planar MOSFET (5). A P type collector layer (8) is provided on the lower surface of the N- type semiconductor substrate (1). The planar MOSFET (5) has an N+ type emitter layer (10), an upper section of the N- type semiconductor substrate (1), a P type base layer (12), and a planar gate (14), which is provided on the N+ type emitter layer, the upper section of the N- type semiconductor substrate, and the P type base layer with a gate insulating film (13) therebetween. The planar gate (14) is connected to a gate trench (4). The P+ type emitter layer (6) has an impurity concentration higher than that of the P type base layer (12), and has an emitter potential equal to that of the N+ type emitter layer (10). The N+ type emitter layer (10) is not in contact with the trench (2), and a trench-type MOSFET is not configured.

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CHEN ZE (JP)

PCT/JP2014/063602

November 26, 2015

May 22, 2014

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MITSUBISHI ELECTRIC CORP (JP)

H01L29/739; H01L29/78

US6303410B1	2001-10-16
JPH05347414A	1993-12-27
JP2003224278A	2003-08-08
JP2008141056A	2008-06-19
JP2007088010A	2007-04-05

TAKADA, Mamoru et al. (JP)
Takada 守 (JP)

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