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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/043425
Kind Code:
A1
Abstract:
A semiconductor device having a plurality of memory cells (MC1, MC2), the semiconductor device being such that each of the plurality of memory cells (MC1, MC2) respectively has: a memory transistor (10M) having an oxide semiconductor layer (17M) as an active layer; and a first selection transistor (10S) having a crystalline silicon layer (13S) as the active layer, and connected in series to the memory transistor (10M).

Inventors:
YAMAMOTO Kaoru
Application Number:
JP2017/030781
Publication Date:
March 08, 2018
Filing Date:
August 28, 2017
Export Citation:
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Assignee:
SHARP KABUSHIKI KAISHA (1 Takumi-cho, Sakai-ku Sakai Cit, Osaka 22, 〒5908522, JP)
International Classes:
H01L27/10; G11C17/06; H01L29/786; H01L45/00; H01L49/00
Domestic Patent References:
WO2015072196A12015-05-21
WO2013080784A12013-06-06
WO2014061633A12014-04-24
Foreign References:
JP2010003910A2010-01-07
JP2014007399A2014-01-16
JP2008153351A2008-07-03
Attorney, Agent or Firm:
OKUDA Seiji (OKUDA & ASSOCIATES, 10th Floor Osaka Securities Exchange Bldg., 8-16, Kitahama 1-chome, Chuo-ku, Osaka-sh, Osaka 41, 〒5410041, JP)
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