Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/092787
Kind Code:
A1
Abstract:
A gate electrode (4a) at a gate potential (G) is provided, via a gate insulating film (3a), in a gate trench (2a) among a plurality of trenches (2) that are disposed in stripe shapes parallel to the front surface of a semiconductor substrate (10). In a dummy trench (2b), a dummy gate electrode (4b) at an emitter potential (E) is provided via a dummy gate insulating film (3b). In a first mesa region (9a) among mesa regions (9), said first mesa region functioning as a MOS gate, a first p-type base region (5a) is provided on the whole surface region, and in a second mesa region (9b) not functioning as the MOS gate, second p-type base regions (5b) are selectively provided at predetermined intervals (D1) in the first direction (X). At least one of the trenches (2) on both the sides of each of the mesa regions (9) is the gate trench (2a), and the MOS gate is driven at least on one side-wall side of the gate trench (2a). Consequently, on-voltage can be reduced.
Inventors:
ABE HITOSHI (JP)
FUJII TAKESHI (JP)
OBATA TOMOYUKI (JP)
FUJII TAKESHI (JP)
OBATA TOMOYUKI (JP)
Application Number:
PCT/JP2017/041001
Publication Date:
May 24, 2018
Filing Date:
November 14, 2017
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L29/739; H01L29/78
Foreign References:
| JP2013183143A | 2013-09-12 | |||
| JP2002016252A | 2002-01-18 | |||
| JP2008021930A | 2008-01-31 | |||
| JP2014112625A | 2014-06-19 | |||
| JP2002538602A | 2002-11-12 | |||
| JP2014075582A | 2014-04-24 |
Attorney, Agent or Firm:
SAKAI, Akinori (JP)
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