Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/065208
Kind Code:
A1
Abstract:
According to the present invention, in order to reduce the power consumption of a semiconductor device by steepening the rise of a drain current when a field-effect transistor has a gate voltage lower than a threshold value, a fully depleted MOSFET, in which a semiconductor layer having a thickness of 20 nm or less serves as a channel region, is configured to have a gate plug which is connected to a gate electrode and which comprises a first plug, a ferroelectric film, and a second plug that are sequentially laminated on the gate electrode. In this configuration, the overlapping area size in planar view between the contact surface of the ferroelectric film to the first plug and the contact surface of the ferroelectric film to the second plug, is smaller than the overlapping area size between the gate electrode and the semiconductor layer serving as an active region.
Inventors:
OTA HIROYUKI (JP)
MIGITA SHINJI (JP)
MIGITA SHINJI (JP)
Application Number:
PCT/JP2018/033568
Publication Date:
April 04, 2019
Filing Date:
September 11, 2018
Export Citation:
Assignee:
AIST (JP)
International Classes:
H01L21/336; H01L21/768; H01L23/522; H01L29/41; H01L29/423; H01L29/49; H01L29/78; H01L29/786
Domestic Patent References:
| WO2015059986A1 | 2015-04-30 | |||
| WO2004019414A1 | 2004-03-04 |
Foreign References:
| US20160336312A1 | 2016-11-17 | |||
| US20170162702A1 | 2017-06-08 |
Attorney, Agent or Firm:
TSUTSUI & ASSOCIATES (JP)
Download PDF:
Previous Patent: WIRE HARNESS ROUTING DEVICE
Next Patent: PREPREG RESIN COMPOSITION, PREPREG, AND MOLDED ARTICLE
Next Patent: PREPREG RESIN COMPOSITION, PREPREG, AND MOLDED ARTICLE