Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/069416
Kind Code:
A1
Abstract:
A super junction layer (90) in the present invention contains: first pillars (3) having a first conductivity type; and second pillars (4) having a second conductivity type. A first well (5a) is provided on each of the second pillars (4), reaches the first pillars (3), and has the second conductivity type. A first impurity region (6a) is provided on each of the first wells (5a), and has the first conductivity type. A second well (5b) is provided on each of the first pillars (3), is disposed separated from the second pillar (4) in a cross section of an active region that is perpendicular to a semiconductor layer (1), and has the second conductivity type. A second impurity region (6b) is provided on each of the second wells (5b), and has the first conductivity type.
Inventors:
FURUHASHI MASAYUKI (JP)
FUJIWARA NOBUO (JP)
KAWABATA NAOYUKI (JP)
FUJIWARA NOBUO (JP)
KAWABATA NAOYUKI (JP)
Application Number:
PCT/JP2017/036213
Publication Date:
April 11, 2019
Filing Date:
October 05, 2017
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L29/739; H01L21/336; H01L29/12; H01L29/78
Domestic Patent References:
| WO2015040938A1 | 2015-03-26 |
Foreign References:
| JP2008091450A | 2008-04-17 | |||
| JP2012160752A | 2012-08-23 | |||
| JP2015216182A | 2015-12-03 | |||
| JP2017168666A | 2017-09-21 | |||
| JP2012064908A | 2012-03-29 | |||
| JP2010040975A | 2010-02-18 | |||
| JP2007194585A | 2007-08-02 |
Attorney, Agent or Firm:
YOSHITAKE Hidetoshi et al. (JP)
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