Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/135333
Kind Code:
A1
Abstract:
[Problem] To maintain the mechanical strength and reliability and reduce the inter-wire capacitance of a semiconductor device. [Solution] A semiconductor device comprising: a multilayer wiring layer having a plurality of interlayer films and a plurality of diffusion-preventing films laminated in an alternating manner, and having wiring provided inside the interlayer films; a contact via provided penetrating a via insulating layer provided on one surface of the multilayer wiring layer, said contact via being electrically connected to the wiring in the multilayer wiring layer; a through-hole provided penetrating at least one of the interlayer films and the diffusion-preventing films, from another surface on the reverse surface from the one surface of the multilayer wiring layer; and a gap connected to the through-hole and provided in at least one interlayer film so as to expose the contact via.
Inventors:
KAWASHIMA HIROYUKI (JP)
Application Number:
PCT/JP2018/044305
Publication Date:
July 11, 2019
Filing Date:
November 30, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/768; H01L21/3205; H01L23/532
Domestic Patent References:
| WO2016158440A1 | 2016-10-06 |
Foreign References:
| JP2002353303A | 2002-12-06 | |||
| JP2014154886A | 2014-08-25 | |||
| JPH10294316A | 1998-11-04 | |||
| JP2001110745A | 2001-04-20 | |||
| JP2001217312A | 2001-08-10 | |||
| JP2015038931A | 2015-02-26 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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