Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/150856
Kind Code:
A1
Abstract:
This semiconductor device comprises a stacked structure in which channel forming region layers CH1, CH2 and gate electrode layers G1, G2, G3 are alternately stacked on a substrate 50. A lowermost layer of the stacked structure is occupied by a first-layer gate electrode layer G1. An uppermost layer of the stacked structure is occupied by an Nth-layer (N ≥ 3) gate electrode layer G3. Each of the gate electrode layers includes a first end surface 11, a second end surface 12, a third end surface 13, and a fourth end surface 14. The first end surface 11 and the third end surface 13 are opposed to each other. The second end surface 12 and the fourth end surface 14 are opposed to each other. The first end surfaces 11 of the odd-numbered gate electrode layers G1, G3 are connected to a first contact portion 41. The third end surface 13 of the even-numbered gate electrode layer G2 is connected to a second contact portion 42.
Inventors:
FUKUZAKI YUZO (JP)
Application Number:
PCT/JP2018/047706
Publication Date:
August 08, 2019
Filing Date:
December 26, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L29/06; H01L29/786; H01L29/16; H01L29/20
Domestic Patent References:
| WO2008023776A1 | 2008-02-28 |
Foreign References:
| US20170365661A1 | 2017-12-21 | |||
| US20170263728A1 | 2017-09-14 | |||
| JP2015195405A | 2015-11-05 |
Other References:
See also references of EP 3748688A4
Attorney, Agent or Firm:
YAMAMOTO Takahisa et al. (JP)
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