Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/150947
Kind Code:
A1
Abstract:
This semiconductor device has a structure formed by alternately disposing, in parallel, N layers of gate electrode layers G and (N-1) layers of channel forming region layers CH (where N≥3) on an insulating material layer 61 of a substrate where the insulating material layer 61 is formed on the surface of a conductive substrate 60. The structure, the channel forming region layers CH, and the gate electrode layers G each have a bottom surface, a top surface, and four side surfaces. A second surface 32 and a fourth surface 34 of the n-th channel forming region layer respectively contact the fourth surface 24 of the n-th gate electrode layer and the second surface 22 of the (n+1)-th gate electrode layer. One of an odd-numbered gate electrode layer and an even-numbered gate electrode layer is connected to a first contact part, and the other is connected to a second contact part.
Inventors:
FUKUZAKI YUZO (JP)
FUKUMOTO KOJI (JP)
FUKUMOTO KOJI (JP)
Application Number:
PCT/JP2019/001056
Publication Date:
August 08, 2019
Filing Date:
January 16, 2019
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L29/786
Foreign References:
| JP2005072582A | 2005-03-17 | |||
| JP2008306172A | 2008-12-18 | |||
| US20170365661A1 | 2017-12-21 | |||
| US20170263728A1 | 2017-09-14 |
Attorney, Agent or Firm:
YAMAMOTO Takahisa et al. (JP)
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