Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/028680
Kind Code:
A1
Abstract:
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises an arithmetic logic unit, bus wiring, and a storage device. The storage device comprises a first element layer having a plurality of readout circuits, and a second element layer having a plurality of cell arrays. Each of the readout circuits has a sense amplifier. Each of the cell arrays has a memory cell. The second element layer is stacked on top of the first element layer. The memory cell and the sense amplifier are electrically connected through a bit line. The storage device is electrically connected to the arithmetic logic unit through the bus wiring. Data retained in one of the plurality of cell arrays is output onto the bus wiring through one of the plurality of readout circuits. The data that is output onto the bus wiring is output with a bit width that is a multiple of eight bits.
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| JPS58130491 | EXTERNAL STORAGE DEVICE |
| JPS5840344 | [Title of the Invention] Semiconductor memory device |
Inventors:
YAMAZAKI SHUNPEI (JP)
MATSUZAKI TAKANORI (JP)
KIMURA HAJIME (JP)
KOBAYASHI HIDETOMO (JP)
INOUE HIROKI (JP)
OKAMOTO YUKI (JP)
MATSUZAKI TAKANORI (JP)
KIMURA HAJIME (JP)
KOBAYASHI HIDETOMO (JP)
INOUE HIROKI (JP)
OKAMOTO YUKI (JP)
Application Number:
PCT/IB2023/057377
Publication Date:
February 08, 2024
Filing Date:
July 20, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
G11C5/02; G06F12/00; G06F12/04; G06F12/06; G06F13/16; G11C5/04; H10B12/00; H10B80/00
Foreign References:
| JPH0567030A | 1993-03-19 | |||
| JP2019061677A | 2019-04-18 |
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