The invention relates to semiconductor devices and methods of making semiconductor devices. In particular the invention relates to the production of semiconductor devices which include a layer of gallium nitride, and to improvements in the crystal structure of such devices.

The devices can be used for a large number of applications, for example, in the formation of light emitting diodes and solid state lasers as well as in electricity generation such as in solar cells, and also in various detectors and other electronic devices for example for use in power electronics. Developments in solid-state lighting are occurring at pace and will lead to near-ultimate lighting sources, mainly based on group Ill-nitride materials. This will result in a fundamental change in the concept of illumination and has the potential to lead to massive savings in energy, estimated to be equivalent to $ 1 12 billion by the year 2020. Such increases in efficiency are increasingly important due to the growing world-wide energy-crisis and threat of global warming.

Currently, there are three main approaches for the fabrication of white light emitting diodes (LEDs) needed for solid-state lighting: ( 1 ) a package of three LED chips each emitting at a different wavelength (red, green and blue, respectively); (2) a combination of a blue (460 nm) LED and a yellow phosphor pumped by blue light from the LED; (3) a single chip emitting UV light which is absorbed in the LED package by three phosphors (red, green and blue) and reemitted as a broad spectrum of white light. Due to the poor performance of current UV emitter, the 3 ^rd method becomes less-impressive. For the 1 ^st and 2 ^nd approaches, the key components are blue/green LEDs, both of which are based on InGaN material systems.

Advanced growth technologies for InGaN-based devices have been well established, but are generally based on c-face sapphire substrates. This polar orientation results in intense built-in electric field due to piezoelectric effects and the devices suffer from reduced overlap between the electron and hole wavefunctions and a long radiative recombination times, and thus low quantum efficiency. This is the so-called quantum confined Stark effect (QCSE). In particular, when the emitters move towards the green spectral region, much higher InN fractions are required and the internal electric fields generally become extremely high. This presents a major obstacle to achieving InGaN- based emitters (in particular, green emitter) with high performance.

One of the most promising approaches to counteract the negative effects of the QCSE is growth along non-polar or semi-polar orientations, as confirmed theoretically and experimentally. Another major advantage of non-polar or semi-polar Ill-nitride emitters is that they can emit polarized light. Liquid-crystal displays (LCDs) require polarized illumination and current LCDs require an extra polarizing element to achieve this. The low transmission efficiency of the polarizer leads to lower efficiency and a device emitting polarized light is advantageous.

Very recently Ill-nitride growth on non-polar or semi-polar planes has led to major breakthroughs for green emitters. However, a major challenge has also been exposed, as these non-polar or semi-polar Ill-nitride emitters with high performance are exclusively grown on extremely expensive GaN substrates (see e.g. K Okamoto, J Kashiwagi, T Tanaka and M Kubota, Appl. Phys. Lett. 94 071 105 (2009); Y Yoshizumi, M Adachi, Y Enya, et al, Applied Physics Express 2 092101 (2009) ; Y Enya, et al, Applied Physics Express 2 082101 (2009) ; H Zhong, A Tyagi, N N Fellows, R B Chung, M Saito, et al, Electron. Lett. 43 825 (2007). Unfortunately, non-polar or semi-polar GaN substrates are very small and extremely expensive . In addition, being highly non-uniform also makes them unsuitable for mass production.

Therefore, it is necessary to obtain non-polar or semi-polar GaN with high crystal template on sapphire substrates with any size (such as up to 12") for further growth of InGaN-based device structures.

Previously, the applicant developed so-called high temperature (HT) AIN buffer for growth of high quality GaN (polar, non-polar and semipolar) on sapphire (c-plane, R- plane or M-plane), (see e.g. F Ranalli, P J Parbrook, J Bai, K B Lee, T Wang and A G Cullis, Phys. Stat. Sol. C 6, S780 (2009); K Xing, Y Gong, J Bai and T Wang, Appl. Phys. Lett. 99, 181907 (201 1); K Xing, Y Gong, X Yu, J Bai, and T Wang, Jpn J. Appl. Phys. 52, 08JC03 (2013); J Bai, T Wang, I M Ross, P J Parbrook and A G Cullis, J. Cryst. Growth 289, 63-67 (2006)) leading to significant improvement in crystal quality of GaN grown on the top of the HT AIN buffer layer, compared with the GaN grown using a standard two-step growth approach (a thin GaN nucleation layer prepared at a low temperature, 500-600 C, followed by a GaN layer grown at a high temperature above 1 100°C).

In the applicant's previous approach for growth of non-polar GaN on R-plane sapphire or semi-polar GaN on m-plane sapphire, the sapphire was initially annealed at 1 100°C or above under flowing H2. Subsequently, an A1N layer with a thickness ranging from 100 nm to 1 μιη was prepared at a temperature above 1 100°C, followed by growth of a thick GaN grown under standard conditions. The growth conditions for GaN are similar to those for growth of the non-polar GaN or semi-polar GaN using the standard two-step approach.

One of the great challenges in growth of non-polar or semi-polar GaN is due to anisotropy in atomic diffusion length. The invention provides a method of making a semiconductor device, the method comprising providing a substrate and growing a layer of GaN on the substrate. The method may comprise forming a buffer layer over the substrate before the GaN layer is grown. The buffer layer may comprise a layer of A1N. The GaN layer may include a component of aluminium.

The aluminium component may make up at least 1 %, or at least 2% by mass of the GaN layer. The aluminium may make up no more than 10%, or no more than 5% by mass of the GaN layer. The A1N layer may have a thickness ranging from 100 nm to 1 μιη.

The substrate may be sapphire, for example c-plane, or R-plane or M-plane sapphire, or it may be silicon or silicon carbide . The GaN may be non-polar or semi-polar GaN. The GaN layer may be grown by exposing the substrate to ammonia and trimethylgallium (TMG). The aluminium may be included in the GaN layer by exposing the substrate to trimethylaluminium (TMA), for example simultaneously with the TMG and ammonia. The addition of a small amount of TMA (Al precursor) flow can reduce the anisotropic issue . However, in the case of using a high TMA flow rate, it will limit atomic diffusion length significantly, leading to a degraded crystal quality of the final semi- polar or non-polar GaN layer. Therefore the amount of TMA used, and hence the aluminium content of the GaN layer, needs to be limited.

The device may be an LED. The GaN layer may therefore comprise a lower GaN layer and the device may further comprise an emitting layer and an upper GaN layer over the lower GaN layer. The upper GaN layer may be formed in the same way as the lower GaN layer. Alternatively the device may be another type of light emitting device such as a laser diode, or a photovoltaic device such as a solar cell or light detector. Indeed, the device may be any other form of electronic device in which is partly formed of GaN and in which crystal quality is a significant factor. In other applications the GaN layer can is used as a template for the bulk growth of non-polar or semi-polar GaN.

The method may further comprise etching the GaN layer or the upper GaN layer, or the upper and lower GaN layers to form an array of nano-columns. This may be achieved by the method including forming a mask over the GaN layer and then etching through the GaN layer to form the nano-columns. The mask may be formed form a first mask layer and a second mask layer.

The first mask layer may be formed of at least one of silicon dioxide and silicon nitride. The second mask layer may comprise a metal, such as nickel, and may be annealed to form islands. The islands may form a mask for etching the first mask layer to form a nano-column mask. The nano-column mask may then be used as a mask for etching the GaN layer.

The present invention further provides a semiconductor device comprising a substrate, a buffer layer of A1N over the substrate, and a GaN layer over the buffer layer, wherein the GaN layer includes aluminium in the range 1 % to 10% by mass.

The device may comprises an array of nano-columns and the GaN layer may form part of each of the nano-columns. The method or device may further comprise, in any combination, any one or more of the steps or features of the preferred embodiments of the invention, which will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 is a schematic section through an LED according to an embodiment of the invention;

Figures 2a to 2e show the steps in the formation of a the nano-rod array in the LED of Figure 1 ;

Figure 3 is a graph showing FWHM of X-ray diffraction rocking curves as a function of azimuth angle for GaN crystals grown with and without TMA; and Figure 4 shows photoluminescence spectra for the GaN layers with and without aluminium content, respectively

Referring to Figure 1 , as an example of a device that is partly formed of GaN, a light emitting diode device according to an embodiment of the invention comprises a substrate 10, which in this case comprises a layer of sapphire, with a semi-conductor diode system 12 formed on it. The diode system 12 comprises a lower layer 14 and an upper layer 16, with emitting layers 18 between them. The lower layer 14 is an n-type layer formed of n-doped gallium nitride (n-GaN), and the upper layer 16 is a p-type layer formed of p-doped gallium nitride (p-GaN). The emitting layers in this embodiment are formed of In _x Gai_ _x N which forms In _x Gai_ _x N quantum well (QW) layers and In _y Gai_ _y N which forms barrier layers (where x>y, and x or y from 0 to 1) . These therefore provide multiple quantum wells within the emitting layers 18. In another embodiment, there is a single In _z Gai_ _z N layer (z from 0 to 1) which forms a single emitting layer.

When an electric current passes through the semiconductor diode system 12, injected electrons and holes recombine in the emitting layers 18 (sometimes referred to as active layers), releasing energy in the form of photons and thereby emitting light. The p-type layer 16 and n-type layer 14 each have a larger band gap than the emitting layers. Structurally the semi-conductor diode system 12 comprises a continuous base layer 20 with a plurality of nano-pillars 22 projecting from it. The n-type layer 14 makes up the base layer and the lower part 24 of the nano-pillars, the p-type layer 16 makes up the upper part 26 of the nano-pillars, and the emitting layers 18 make up an intermediate part of the nano-pillars 22. Therefore the p-type layer 16, the emitting layers 18, and part of the n-type layer are all discontinuous, and the base layer 20 closes the bottom end of the gaps 30. The nano-pillars 22 are of the order of hundreds of nanometers in diameter, i.e . between 100 and l OOOnm.

The gaps 30 in the discontinuous layers, between the nano-pillars 22, can be filled with a simple filler, or with various materials to enhance the luminosity of the device and/or modify the spectral content of the emitted light. In this case the gaps 30 are filled with a mixture 3 1 of wavelength-conversion material 32 (which could be an insulating transparent material or semi-insulating transparent material) 32 and metal particles 34. Thus the wavelength-conversion material acts as a support material to support the metal particles 34 in the gaps 30. This mixture 3 1 fills the gaps 30 and forms a layer from the base layer 20 up to the top of the nano-pillars 22. In this embodiment it will be appreciated that the gaps 30 are in fact joined together to form one interconnected space that surrounds all of the nano-pillars 22. If the nano-pillars 22 are formed so that the maximum distance between adjacent nano-pillars 22 is, say, 200 nm then the maximum distance from any one of the metal particles 34 to a surface of one of the nano-pillars 22 is 100 nm. In which case, any of the metal particles 14 that is coplanar with the emitting layers 18 is in a position which permits surface plasmon coupling. Moreover, the metal particles 14 are suspended in the wavelength conversion material 32 and distributed randomly throughout it. Therefore, in this case, most of the particles 14 will be positioned less than 100 nm (and for some particles, effectively zero nm) from a surface of one of the nano-pillars 22. The wavelength-conversion material 32 in this case is a polymer material, but could be a phosphor; in addition, cadmium sulphide may be used but many suitable types of wavelength-conversion material 32 will be apparent to those skilled in the art.

The metal particles 34 are silver. The size of the metal particles 34 is from a few nm to about 1 μιη, depending in part on the size of the pillars, and the particle concentration in the wavelength-conversion material 32 is from 0.0001 %w/w up to 10%w/w. In other embodiments the metal particles 34 can be gold, nickel or aluminium, for example. The choice of metal is based on the wavelength, or frequency of light from the emitting layers 18; for example silver is preferred for blue LEDs but aluminium is preferred for ultraviolet LEDs.

Because the gaps 30 extend through the emitting layers 18, parts of the sides of the gaps 30 are formed by the emitting layer material, so the emitting layer material is exposed to the gaps 30. The mixture 3 1 is positioned directly adjacent or in contact with the sides of the gaps 30 i.e. there are no insulating layers or other materials positioned in the gaps 30 between the mixture 3 1 and the sides. Therefore some of the metal particles 34 suspended in the mixture 3 1 are a near field distance (47 nm or less) from an exposed surface of the emitting layers, which permits improved surface plasmon coupling. Some of the metal particles 34 are suspended in the mixture 3 1 such that they are very near, or even in contact with, an exposed surface of the emitting layers 18. Also the polymer wavelength-conversion material 32 is close to, and in contact with, the exposed parts of the emitting layers 18. That is, the distance from an exposed surface of the emitting layers 18 to at least some of the metal particles 34, and to the wavelength conversion material 32, is effectively zero.

In another embodiment the polymer wavelength material is used, but the metal nano- particles are omitted.

A transparent p-contact layer 40 extends over the tops of the nano-pillars 22, being in electrical contact with them, and also extends over the top of the gaps 30 closing their top ends. A p-contact pad 42 is formed on the p-contact layer 40. A portion 44 of the base region 14 extends beyond the nano-pillars 22 and has a flat upper surface 46 on which an n-contact 48 is formed. Referring to Figure 2a, the first step of fabricating a nano-rod array, suitable for use as the nano-pillars or rods 22 that form the basis of the device of Figure 1 , is providing a suitable semiconductor wafer 201. The wafer 201 is made up of a substrate 205, which in this case comprises a layer of sapphire, over which is an aluminium nitride (A1N) buffer layer 206, and then a semiconductor layer 210 formed of the lower and upper gallium nitride (GaN) layers 210a, 210b with InGaN emitting layers 210c between them. The lower layer 210a is an n-type layer formed of n-doped gallium nitride (n-GaN), and the upper layer 210b is a p-type layer formed of p-doped gallium nitride (p-GaN). For growth of non-polar GaN on R-plane sapphire or semi-polar GaN on m-plane sapphire, the sapphire is initially annealed at 1 100°C or above under flowing H2. Subsequently, an AIN layer with a thickness ranging from 100 nm to 1 μιη is prepared at a temperature above 1 100°C. Then the lower GaN layer 210a is grown over the AIN layer. This is achieved by passing trimethylgallium (TMG) in a carrier gas, which in this case is hydrogen, and ammonia, over the substrate so that they react to form the GaN. The conditions of this reaction are standard, except that in addition to the TMG, a small quantity of trimethylaluminium (TMA) is added to the gas flow so that the AIN layer is exposed to the TMG and TMA simultaneously. This results in the GaN layer containing a small quantity of aluminium. The relative amounts of TMA and TMG can be varied to vary the amount of aluminium present in the resulting GaN crystal. Aluminium content of 1 % to 10% by mass is sufficient in some cases, and from 2% to 5% in some cases. For example 3% of Al by mass was used in the examples described in the tests below. The GaN layer formed in this way can be used for a number of applications. In this embodiment, it is used to form an LED, as described above with reference to Figure 1 , from the semiconductor wafer as will now be described. A first mask layer 220 is provided over the semiconductor layer 210, for example using plasma-enhanced chemical vapour deposition (PECVD). The first mask layer 220 is formed of silicon dioxide, although there are suitable alternative materials for this layer e.g. silicon nitride, and is deposited at an approximately uniform thickness of 200 nanometres. A thicker layer, for example up to 600nm, can be used.

In an optional additional step, a layer of indium tin oxide (ITO) is applied to the semiconductor (GaN) layer before the silicon dioxide . The ITO layer is preferably about 20nm thick. The ITO layer can act as a protective layer for the GaN during subsequent etching of the silicon dioxide .

A metal layer 230 comprising a metal, in this case nickel, is formed over the first mask layer 220. The metal layer can be formed by thermal evaporation or sputtering or electron beam evaporation. The nickel layer is of approximately uniform thickness in the range 5 to 50 nanometres, preferably 5 to 25nm. After the metal layer 230 has been formed it is annealed under flowing nitrogen (N ₂ ), at a temperature in the range 600 to 900, preferably 700 to 850 degrees Celsius. The duration of the annealing process is between 1 and 10 minutes. The annealing results in formation from the nickel layer of a layer 230 comprising self-assembled nickel islands 23 1 distributed irregularly over the first mask layer 220 as shown in Figure 2b to form a second mask layer. Each of the nickel islands 23 1 covers a respective, approximately circular, area of the upper surface of first mask layer 220 which is, typically, no less than 100 nanometres in diameter and no more than 1500 nanometres in diameter.

Then the second mask layer 230 can act as a mask for etching the underlying Si0 ₂ layer, in which the nickel islands 232 mask areas of the underlying Si0 ₂ layer and the spaces between the nickel islands leave exposed areas of the Si0 ₂ layer, defining which areas of the underlying Si0 ₂ layer will be etched. If the ITO layer is present during this step, it protects the GaN during etching of the Si0 ₂ layer.

With reference to Figure 2c, the first mask layer 220 is etched through using CHF ₃ or SF ₆ in a reactive ion etching (RIE) process using the metal islands 23 1 of the second mask layer 230 as a mask. This step provides nano-pillars (also referred to as nano- rods) 240 of silicon dioxide distributed irregularly over the GaN layer 210, each comprising a respective part 221 of the first mask layer 220 and a respective nickel island 232. Each nano-rod 240 corresponds to a respective nickel island, having a diameter that is approximately the same as the diameter of the surface area covered its respective nickel island. The nano-pillars 240 resulting from the previous step serve to mask some areas of the GaN layer 210, and to define which areas (i.e. those exposed areas in the spaces between the nano-pillars 240) of the GaN layer 210 will be etched.

Referring to Figure 2d, at the next step the GaN layer 210 is etched, for example by inductively coupled plasma etching, with the nano-pillars 240 that were formed in the previous steps used as a mask. This step involves etching though the GaN layer 210, such as shown in Figure 2d, or partly through the GaN layer 210. This step results in a nano-pillar structure, as shown in Figure 2d, in which nano-pillars 250 extend upwards from the sapphire substrate 205, each nano-pillar 250 comprising a respective part 21 1 of the GaN layer 210, a part 221 of the first mask layer 220, and a metal island 232 from the second mask layer 230. The diameter of each nano-pillar 250 is approximately constant from top to bottom, being approximately the same as the diameter of the surface area covered by its respective nickel island 232, although in practice some tapering of the nano-pillars generally occurs.

Referring to Figure 2e, the nickel islands 232 forming the second mask layer 230 are then removed, leading to the nano-pillar 260 comprising a respective part 21 1 of the GaN layer or layers 210, a part 221 of the first mask layer 220. This can be done by wet etching using hydrochloric acid (HCl) or nitric acid (HN0 ₃ ). This leaves each nano-pillar comprising mainly a GaN column 21 1 , which has an emitting layer 21 1c part way down between its top and bottom ends 21 1a, 21 1b, with a Si0 ₂ cap 221 on its top end.

Referring back to Figure 1 , once the nano-pillar structure has been formed, a standard photolithography can be carried out in order to have the region 44 of the base layer with a flat upper surface 46 on which the n-type contact can be formed. The mixture 3 1 of a wavelength-conversion material 32, and metal particles 34 is inserted into the gaps 30 by spin coating. This mixture 3 1 is added into the gaps 30 until they are full up to the level of the tops of the nano-pillars 22, and then any surplus is removed so that the top of the mixture 3 1 and the top of the non-pillars 22 form a substantially flat surface .

The transparent p-contact layer 40 is then formed over the top of the pillars 22, closing the top end of the gaps 30 and making electrical contact with the tops of the nano-pillars 22. Finally the p-contact pad 42 is formed on the p-contact layer 40, and the n-contact 48 is formed on the flat surface 46.

In operation, when an electrical potential is applied across the p- and n-contacts 42 and 48, light of one wavelength or wavelength spectrum, in this case predominantly blue, is emitted from the emitting layers 18. Some of this light is absorbed by the wavelength-conversion material 32, and re-emitted as light of a different wavelength or wavelength spectrum, in this case yellow light. The blue and yellow light together produce light of a sufficiently broad spectrum for it to be white . The nano-pillar structure is well suited to the production of LEDs, but can be used for various other applications.

Figure 3 shows the comparative XRD data of the two semi-polar GaN samples as examples, the samples grown with and without a small amount of TMA flowing in order to demonstrate the advantages of the invention. For any semi-polar (or non- polar) GaN, the crystal quality can be evaluated by the full-width at half-maximum (FWHM) of XRD rocking curves as a function of azimuth angel. The azimuth angle is normally defined as zero when the projection of the incident x-ray beam is parallel to (0001) direction of the epi-layer. Figure 3 clearly indicates that FWHMs of the sample grown with a small amount of TMA flowing have been massively reduced compared to the sample grown without flowing the small amount of TMA, indicating the dislocation density has been reduced by means of using the invention. Figure 4 shows the photoluminescence (PL) data of the two semi-polar GaN samples grown with and without a small amount of TMA flowing, measured under identical conditions at room temperature. Figure 4 clearly demonstrates that the PL intensity of the sample grown with the small amount of TMA flowing is enhanced by a factor of -30, compared with the sample grown without with the small amount of TMA flowing. It will be noted that the emission peak is at 355 nm for the sample grown with the small amount of TMA flowing, corresponding to the GaN layer containing -3% of Al composition, while the emission peak for the sample without the small amount of TMA flowing is at 363 nm, the typical band-edge emission energy of GaN on sapphire. This shows that the inclusion of TMA in the process of growing the GaN leads to a significant increase in crystal quality and thus optical performance .

It will be appreciated that other embodiments of the invention can differ from those described above . For example the method can be used for growth of non-polar GaN on other foreign substrates, such as silicon, SiC, etc. Also, in other embodiments the GaN layer, once grown on the substrate, is used in the production of a laser diode, a photocell, and a photodetector respectively. As mentioned above, other electronic components, for example for use in power electronics, can also be produced from the GaN wafer and benefit from the improved crystal structure. Also the GaN layer can be used as a template for further growth of semiconductor materials, for example of bulk non-polar or semi-polar GaN.