CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority under 35 U. S. C. § 119(e) to U.S. Provisional Application Serial No. 61/146,710, filed January 23, 2009, which is hereby incorporated in its entirety by reference.

FIELD OF INVENTION

1. Field of the Invention

[0002] The invention relates generally to semiconductor devices and methods of making the same, and more specifically to light-emitting devices. The semiconductor devices can be metal oxide semiconductor devices, including but not limited to ZnO- based devices.

2. Description of Related Art

[0003] Semiconductor devices, such as opto-electronic devices, electronic devices, and photonic devices, have found utility in a plethora of applications due to their robustness and efficiency. For example, semiconductor light-emitting devices, such as LEDs, can serve as efficient, robust, and long-lasting light sources. Such semiconductor lighting can soon replace incandescent and fluorescent light sources in many if not all applications, thereby providing an efficient and more environmentally- friendly lighting technology.

SUMMARY OF INVENTION

[0004] In one aspect, a semiconductor device comprises a first metal oxide semiconductor layer comprising a first dopant, a second layer, and a first dopant diffusion barrier disposed between the first metal oxide semiconductor layer and the second layer, wherein the first dopant diffusion barrier inhibits diffusion of the first dopant into the second layer.

[0005] In another aspect, a semiconductor device comprises a first metal oxide semiconductor layer comprising a first dopant, said layer having a wurtzite crystal structure and a layer interface oriented substantially parallel to a non-polar plane or semi-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, a second layer having a wurtzite crystal structure and a layer interface oriented substantially parallel to a non-polar plane or semi-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, and a first dopant diffusion barrier disposed between the first metal oxide semiconductor layer and the second metal oxide semiconductor layer, wherein the first dopant diffusion barrier inhibits diffusion of the first dopant into the second layer.

[0006] In another aspect, a light-emitting device comprises a p-type semiconductor layer comprising a p-type dopant, an n-type semiconductor layer comprising an n-type dopant, an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer, wherein the active layer has a wurtzite crystal structure, and wherein the active layer has layer interfaces orientated substantially parallel to a non-polar plane or a semi-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, and a first strained layer disposed between the p-type semiconductor layer and the active layer.

[0007] In any of the preceding embodiments, the metal oxide of the metal oxide semiconductor layer includes zinc oxide, and/or the second layer is selected from the group consisting of an insulating layer, a p-type semiconductor layer, an n-type semiconductor layer, and an intrinsic semiconductor layer.

[0008] In any of the preceding embodiments, the second layer includes an n-type metal oxide semiconductor, the first layer is a p-type metal oxide semiconductor layer, and an active layer is disposed between the first dopant diffusion layer and the second layer.

[0009] In any of the preceding embodiments, the first metal oxide semiconductor layer and the second layer have a larger bandgap than at least a portion of the active layer.

[0010] In any of the preceding embodiments, at least a portion of the first dopant diffusion barrier has a same conductivity type as the first metal oxide semiconductor layer.

[0011] In any of the preceding embodiments, the first dopant is a p-dopant and the first layer is a p-type metal oxide semiconductor layer.

[0012] In any of the preceding embodiments, the first dopant diffusion barrier is a strained metal oxide semiconductor layer, and optionally, the strained metal oxide semiconductor layer is compressively strained or tensilely strained.

[0013] In any of the preceding embodiments, at least a portion of the first dopant diffusion barrier is a carrier blocking layer.

[0014] In any of the preceding embodiments, the strain is in the range of about

0.1% to about 1%, or at least 0.1%, or at least 0.4 %, or at least 1.0 %. [0015] In any of the preceding embodiments, the strain comprises an in-plane lattice mismatch of the first dopant diffusion barrier layer with the first metal oxide semiconductor layer.

[0016] In any of the preceding embodiments, the diffusion barrier layer has a thickness of less than 100 nm, or less than 50 nm, or less than 25 nm, or less than 10 nm.

[0017] In any of the preceding embodiments, the first dopant is a Group IA element, or the first dopant is a Group IB element, or the first dopant is a Group V element.

[0018] In any of the preceding embodiments, the first layer has a wurtzite crystal structure and a layer interface oriented substantially parallel to an non-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, or .the first layer has a wurtzite crystal structure and a layer interface oriented substantially parallel to a semi- polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, or the first and second layers have a wurtzite crystal structure and layer interfaces oriented substantially parallel to a non-polar or semi-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure.

[0019] In any of the preceding embodiments, the dopant diffusion barrier has a superlattice structure.

[0020] In any of the preceding embodiments, the device further includes a second dopant diffusion barrier disposed between the second layer and the active layer, wherein the second dopant diffusion barrier inhibits diffusion of an n-dopant of the second layer into the active layer.

[0021] In any of the preceding embodiments, at least a portion of the second dopant diffusion barrier has the same conductivity type as the second layer, and optionally, the second layer comprises zinc oxide.

[0022] In any of the preceding embodiments, the first layer, the second layer and the active layer include one or more ZnO-based semiconductors. [0023] In any of the preceding embodiments, the first dopant diffusion barrier layer includes a zinc oxide alloy formed with alloying elements that are aliovalent with respect to zinc oxide.

[0024] In any of the preceding embodiments, the first dopant diffusion barrier layer comprises a transition metal. [0025] Other aspects, embodiments and features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings. The accompanying figures are schematic and are not intended to be drawn to scale. In the figures, each identical or substantially similar component that is illustrated in various figures is represented by a single numeral or notation. For purposes of clarity, not every component is labeled in every figure. Nor is every component of each embodiment of the invention shown where illustration is not necessary to allow those of ordinary skill in the art to understand the invention. All patent applications and patents incorporated herein by reference are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control.

BRIEF DESCRIPTION OF DRAWINGS [0026] In the drawings:

FIG. 1 is a cross-sectional view of a semiconductor structure including a dopant diffusion barrier, according to one embodiment;

FIG. 2A is a cross-sectional view of a light-emitting device including a dopant diffusion barrier, according to one embodiment;

FIG. 2B is a cross-sectional view of a light-emitting device including a dopant diffusion barrier, according to one embodiment; and

FIG. 3 is a cross-sectional view of a light-emitting device including a dopant diffusion barrier, according to one embodiment.

DETAILED DESCRIPTION

[0027] Semiconductor devices, such as optoelectronic and electronic devices, have the potential to provide high operating efficiency and long operating lifetimes; however a variety of mechanisms can lead to degradation of the semiconductor device efficiency and/or lifetime. For example, in some semiconductor laser diodes, dislocation motion under forward bias, referred to as dark line defects, can be a common failure mode. Other mechanisms can also lead to a reduction in efficiency or lifetime.

[0028] In some semiconductor devices, degradation of semiconductor device efficiency and/or lifetime can be attributed to a variety of mechanisms. One such mechanism is dopant diffusion during fabrication or during device operation (e.g., via dopant electromigration). Dopants utilized to create p-type or n-type semiconductor layers can diffuse into adjacent layers, such as quantum wells in an active layer, and thereby reduce the device efficiency. Dopant diffusion can be particularly fast along certain semiconductor crystal orientations. For example, in the case of a wurtzite crystal system, dopant diffusion can be faster along non-polar axis directions (e.g., perpendicular to the m-plane or a-plane) or semi-polar axis directions than along polar axis directions (e.g., perpendicular to the c-plane). Dopant diffusion can also be particularly fast for specific classes of dopants used for specific semiconductor materials. For example, dopants used in metal oxide semiconductors (e.g., ZnO-based semiconductors), such as Group IA and Group IB metals that can be used as p-dopants in ZnO-based semiconductors, are particularly susceptible to diffusion. Controlling these dopant diffusion rates is one way in which the detrimental effects of dopant diffusion on semiconductor device efficiency and/or lifetime can be mitigated. [0029] Device structures and methods provided herein reduce the extent of dopant diffusion. It has been surprisingly discovered that dopant diffusion even in semiconductor material systems, crystal orientations, and/or dopant types that are prone to rapid diffusion can be inhibited or reduced In some embodiments, dopant diffusion barriers are incorporated into a semiconductor device so as to impede the diffusion of dopants into one or more adjacent layers, such as into quantum wells of an active layer. The structures and processes described can be applied to any suitable semiconductor device, including but not limited to opto-electronic devices, photonic devices, and electronic devices (e.g., LEDs, laser diodes, photodiodes, photovoltaics, excitonic devices, excitonic integrated circuits, excitonic light switches, transistors). [0030] When constructing semiconductor devices for opto-electronic applications and photonic applications, controlling dopant diffusion presents certain challenges. Generally, it is desirable to provide diffusion barriers without impeding the performance of the active layer(s) in the semiconductor devices. For example, it is desirable to include a dopant diffusion barrier that not only inhibits the migration of dopants into an active layer but also appropriately matches the doped region to which it is adjacent. Engineering an appropriate dopant diffusion barrier that can be readily incorporated into either side of a p-n junction device without impeding the junction operation is one objective of the present disclosure. For example, a dopant diffusion barrier thickness that achieves desired blocking for the selected dopants and also serves a function, such as carrier blocking (e.g., electron and/or hole blocking to mitigate electron and/or hole overflow from the active layer), in the electrical operation of the device is contemplated. In certain embodiments, the dopant diffusion barrier layer is selected and deposited so as to provide an appropriately doped or intrinsic strained layer. Strain of the dopant diffusion barrier layer disposed between doped (or intrinsic) regions, attributable in part to the lattice mismatch, can be selectively controlled to achieve the desired dopant diffusion characteristics (e.g. for specific dopants).

[0031] Moreover, there are certain subsets of materials of particular interest in these opto-electronic and photonic applications. For example, metal oxide semiconductors such as ZnO-based semiconductors, can be particularly useful in certain embodiments. In these embodiments, the dopant diffusion barriers are interposed between a p-doped layer and an active layer to inhibit the diffusion of p- type dopants into the active layer. In each case, the dopant diffusion barriers can be used without substantially impacting the desired energy band gap configuration for the electrical operation of the device. The present disclosure discusses dopant diffusion barriers in the example of metal oxide semiconductor devices such as ZnO-based semiconductors, as well as a variety of other semiconductor materials, such as Group III-N semiconductors, that have been found to be useful in different applications. [0032] FIG. 1 illustrates a cross-sectional view of a dopant diffusion barrier of a semiconductor structure 100 that can be part of a semiconductor device. The semiconductor structure includes a first semiconductor layer 108 comprising a first dopant, and a second layer 105. In some embodiments, the first semiconductor layer 108 is a first conductivity type semiconductor layer, and the first dopant is a first conductivity type dopant. In some embodiments, second layer 105 can also be a semiconductor layer having the same or a different conductivity type as first semiconductor layer 108. In some embodiments, second layer 105 is a second conductivity type semiconductor layer comprising a second conductivity type dopant. For example, semiconductor layer 108 can be a p-type semiconductor and layer 105 can be an n-type semiconductor. Alternatively, semiconductor layer 108 can be an n- type semiconductor and layer 105 can be a p-type semiconductor. In some embodiments, layer 105 can be an intrinsic semiconductor layer. In other embodiments, layer 105 is an electrically insulating layer, for example a portion or all of a gate dielectric of a semiconductor device, such as a field effect transistor. In yet other embodiments, layer 105 is a metal layer. [0033] Dopant diffusion barrier 102 is disposed between semiconductor layer 108 and layer 105. Dopant diffusion barrier 102 provides a diffusion barrier for the first dopant and thus inhibits the diffusion of the first dopant (e.g., from semiconductor layer 108) into layer 105. In some embodiments, other layer(s) can be disposed between dopant diffusion barrier 102 and layer 105 and/or dopant diffusion barrier 102 and layer 105.

[0034] In some embodiments, one or more of the layers can be metal oxide semiconductor layers, such as ZnO-based semiconductor layers. Semiconductor layer 108 can be a metal oxide semiconductor layer, such as a ZnO-based semiconductor layer. Additionally, or alternatively, layer 105 and/or dopant diffusion barrier 102 can be metal oxide semiconductor layers, such as a ZnO-based semiconductor layers. In other embodiments, layer 105 and/or dopant diffusion barrier 102 can be formed of materials other than metal oxide semiconductors, such as other semiconductors, insulators, and/or metals.

[0035] Details of various embodiments of the dopant diffusion barrier are discussed hereafter in the context of a light-emitting device (e.g., LED or laser diode), however it should be appreciated that the semiconductor structure 100 of FIG. 1 or the like can be part of any other semiconductor devices, such as other opto-electronic, photonic, and electronic devices.

[0036] FIG. 2A illustrates a cross-sectional view of a light-emitting device 200 including a dopant diffusion barrier, such as an LED or a laser diode. The device 200 includes a first conductivity type semiconductor layer 108 having a first conductivity type dopant, a second conductivity type semiconductor layer 106 having a second conductivity type dopant, and an active layer 104 disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. For example, semiconductor layer 108 can be a p-type semiconductor and semiconductor layer 106 can be an n-type semiconductor. Alternatively, semiconductor layer 108 can be an n-type semiconductor and semiconductor layer 106 can be a p-type semiconductor.

[0037] A first dopant diffusion barrier 102 can be disposed between the first conductivity type semiconductor layer 108 and the second conductivity type semiconductor layer 106, wherein the first dopant diffusion barrier provides a diffusion barrier for the first dopant and thus inhibits the diffusion of the first conductivity type dopant. First dopant diffusion barrier 102 can be disposed between the first conductivity type semiconductor layer 108 and the active layer 104. Dopant diffusion barrier 102 can comprise one or more layers that substantially inhibit the diffusion of the first conductivity dopant. The semiconducting layer 108 can be a layer for which the dopant has a high tendency for diffusion. Diffusion is enhanced by the use of group 1 elements as dopants or by layers in the wurtzite crystal structure having an interface oriented substantially parallel to a non-polar plane or semi-polar plane.

[0038] In some embodiments, the light-emitting device can have a double heterostructure where the first conductivity type semiconductor layer 108 and the second conductivity type semiconductor layer 106 have a larger bandgap than at least a portion or all of the active layer 104. A double heterostructure configuration can be achieved by forming semiconductor layers 106 and 108 from different semiconductor compositions that active layer 104. For instance, active layer 104 can include ZnO or a ZnO-based material including Cd, Se, and/or Te. Such elements can facilitate the modification (e.g., lowering) of the bandgap so as to provide a desired wavelength for the emitted light (e.g., UV-A with an energy less than the bandgap energy of ZnO, or visible light such as blue light). The Cd, Se, and/or Te atomic fraction can be less than about 0.3 and/or can be greater than about 0.05. Such alloys can enable visible light generation (e.g., ranging from about 400 nm to about 700 nm). Semiconductor layers 106 and 108 can include a ZnO-based material including Ca, Mg, and/or Be. For example, layer 106 and 108 can be formed with ZnO, ZnMgO, ZnBeO, ZnSrO and/or ZnCaO to produce light emission at or above the bandgap energy of ZnO (e.g., greater than about 3.37 eV).

[0039] In some such double heterostructures, the dopant diffusion barrier 102 can also have a larger bandgap than the active layer. The dopant diffusion barrier 102 can have a larger bandgap than at least a portion or all of semiconductor layer 108. Alternatively, the dopant diffusion barrier 102 can have a similar or a smaller bandgap than the active layer.

[0040] The light-emitting device can be formed on a substrate 240. Substrate 240 can be electrically insulating or semi-insulating for a lateral contact geometry, as shown in FIG. 2A. Alternatively, substrate 240 can be electrically conductive for a vertical contact geometry where an electrode is disposed on the backside of the substrate. Substrate 240 can be a ZnO-based (e.g., ZnO or ZnO alloy such as ZnMgO), MgO, Ill-nitride (e.g., GaN, AlN), sapphire, SiC, silicon, ScAlMg substrate, or any other suitable substrate. In some embodiments, the substrate can be a single crystal substrate. The substrate can be electrically conductive (e.g., n-type or p-type), optically transparent (e.g., to the wavelength of light emitted by the active layer and/or to all visible wavelengths), and/or thermally conductive. In some embodiments, the substrate comprises a ZnO-based material. Examples of such substrates can include a ZnO single crystal substrate, a substrate including a layer of ZnO disposed on (e.g., deposited on and/or wafer bonded to) another material such as a sapphire base substrate or a glass base substrate, or any other substrate that includes a ZnO-based material.

[0041] The light-emitting device can include a first electrode 220 contacting semiconductor layer 106 and a second electrode 230 contacting semiconductor layer 108. A current spreading layer 210 can be provided between second electrode 230 and semiconductor layer 108 and can provide for effective current spreading across semiconductor layer 108. In some embodiments, the current spreading layer 210 can be a low resistivity semiconductor layer (e.g., low resistivity n-type or p-type semiconductor). Reflective layer 260 can be disposed under substrate 240 to reflect any light emitted by the active layer that is directed into the substrate. Reflective layer 260 can include a reflective metal layer (e.g., a layer comprising Al and/or Ag). [0042] n-Electrodes that provide an Ohmic contact for a ZnO-based device include metal layers with Ti or Cr in contact with an n-type ZnO-based semiconductor layer, such as Ti/ Al, Ti/ Au, Cr/ Al, or Cr/ Au. P-electrodes that provide an Ohmic contact for a p-type ZnO-based semiconductor layer include Ni/ Au, NiO/Ni/Au, or NiO/Au.

[0043] Current spreading layer 210 can be formed of a transparent conducting material, such as a transparent conductive oxide. Examples of transparent conductive oxides can include ZnO-based materials, such as n-doped ZnO-based semiconductors doped or alloyed with n-type dopants (e.g., Al, Ga, and/or In), p-doped ZnO-based semiconductors doped or alloyed with p-type dopants (e.g., K, Au and/or Ag), or other oxides such as In ₂ O ₃ , indium tin oxide (ITO), tin oxide, or any combination thereof. Current spreading layer 210 can have any suitable thickness, with a typical thickness ranging from between about 0.1 microns and about 3 microns, and a preferred thickness of about 1 microns. In some embodiments, the current spreading layer can have a thickness and absorption coefficient so as to exhibit light transmittance of greater than about 60% (e.g., greater than about 70%, greater than about 80%, greater than about 90%) at a wavelength of light emitted by active layer 4. In some embodiments, the current spreading layer, such as a transparent conductive oxide, has a resistivity of less than about 10 ^~2 Ωcm (e.g., less than about 10 ^~3 Ωcm) for an n-type current spreading layer and less than about 1 Ωcm (e.g., less than about 10 ^"1 Ωcm) for a p-type current spreading layer. Current spreading layer 210 can be a single crystalline, polycrystalline, or amorphous. Current spreading layer 210 can be textured so as to enhance light extraction from the surface of the light-emitting device. A textured surface morphology of a layer, such as a current spreading layer 210, can be formed during deposition of the layer and/or after deposition of the layer, for example via chemical etching of the deposited layer. Alternatively, or additionally, one of more of the other device layers (e.g., semiconductor layers 106, 104, 102 and/or 108) can be textured. Examples of texturing process and/or devices including such textured layers are described in U.S. patent application numberl2/562,941, filed September 18, 2009 and entitled "Textured Semiconductor Light-emitting Devices," commonly owned by the assignee and herein incorporated by reference in its entirety. [0044] As shown in FIG. 2B, structure 202 has semiconductor layers 106 and 108 that can be formed of one or more layers. For example, in an LED, semiconductor layers 106 and 108 can include cladding layers 261 and 281, respectively, that sandwich active layer 4, and contact layers 262 and 282 disposed on either side of each cladding layers 261 and 281, respectively. In some embodiments, dopant diffusion barrier 102 can have a larger bandgap than cladding layer 281 and/or cladding layer 261. Contact layers can have a higher dopant concentration than the cladding layers, and can be formed of the same or different semiconductor materials. Other layers can be included, for example, in a laser diode, semiconductor layers 106 and 108 can include optical guiding layers disposed on either side of active layer 4. Others layer can be included to facilitate the layer growth process, for example a buffer layer (not shown) can be deposited on the substrate 240, and the above- mentioned device layers can then be deposited on the buffer layer. [0045] The thickness of semiconductor layer 106 and/or semiconductor layer 108 can range from about 0.5 microns to about 3 microns, however any other suitable thickness can also be used. Doping of semiconductor layer 106 and/or semiconductor layer 108 can be achieved with various dopant elements, as described in detail below. For example, for ZnO-based materials, doping with one or more suitable Group IA, IB, VA and/or VB elements, such as K, Au, Ag, N, P As, Sb and/or other appropriate elements, can be used to achieve p-type conductivity. Doping with one or more suitable Group III elements (e.g., B, Al, Ga, In, and/or Tl) and/or Group VII elements (e.g., F, Cl, Br, I) can be used to achieve n-type conductivity. The doping concentration of part or all of semiconductor layer 106 and/or semiconductor layer 108 can range between from about 10 ¹⁶ cm ^"3 to about 10 ²¹ cm ^"3 , however any other suitable doping concentration can be used.

[0046] Active layer 104 can be a bulk layer, a single quantum well structure, or a multiple quantum well structure that can include barrier layers between the quantum wells. In some embodiments, the thickness of active layer 104 can range from about 2 nm to about 500 nm, and preferably between about 50 nm and about 100 nm (e.g., about 75 nm). Active layer 104 can be at least in part intrinsic, n-doped, and/or p- doped. For example, active layer 104 can comprise one or more quantum wells and barrier layers disposed on either side of each quantum well. Some or all of these layers can be intrinsic layers. For example, the quantum wells and/or the barrier layers can be intrinsic layers. Alternatively, the barrier layers and/or the quantum wells can be doped (e.g., n-doped and/or p-doped). Doping of the barrier layers can enhance device performance by providing electrostatic shielding for any spontaneous polarization fields present in the semiconductor. In some embodiments, active layer 104 can comprise one or more intrinsic layers, for example, one or more intrinsic quantum wells. In such a situation, inhibiting dopant diffusion into the quantum wells can enable reliable device operation.

[0047] In some devices described herein, metal oxide semiconductor materials, such as ZnO-based materials can be employed to form part or the entire semiconductor portion of a semiconductor device (e.g., a light-emitting device). For example, first conductivity type semiconductor layer 108, second conductivity type semiconductor layer 106, diffusion barrier 102, active layer 104, and/or current spreading layer 210 can comprise one or more metal oxide semiconductors. In some embodiments, first conductivity type semiconductor layer 108, second conductivity type semiconductor layer 106, diffusion barrier 102, active layer 104, and/or current spreading layer 210 can each entirely be formed of one or more metal oxide semiconductors (e.g., one or more ZnO-based semiconductors). [0048] For instance, active layer 104 can include a ZnO-based material including Cd, Se, and/or Te. Such elements can facilitate the modification (e.g., lowering) of the bandgap so as to provide a desired wavelength for the emitted light (e.g., visible light such as blue light). The Cd, Se, and/or Te atomic fraction can be less than about 0.3 and/or can be greater than about 0.05. Such alloys can enable visible light generation (e.g., ranging from about 400 nm to about 700 nm). [0049] Barrier layers for the quantum wells can be formed of a material having a larger bandgap that the quantum wells, for example, any suitable ZnO-based material can be used that has such a bandgap. For example, ZnO itself or any suitable ZnO- based materials including Mg, Ca, Be, Sr, Ba, Cd, Se, Te, and/or S can be used as a barrier layer material for one or more of the quantum well barrier layers. [0050] In some embodiments, active layer 104 can include a ZnO-based material having a bandgap corresponding to UV light (e.g., UV-A, UV-B, or UV-C). For example, quantum wells can be formed with ZnO, ZnMgO, ZnBeO, ZnSrO and/or ZnCaO to produce light emission at or above the bandgap energy of ZnO (e.g., greater than about 3.37 eV). In such devices, semiconductor layer 106, semiconductor layer 108, dopant diffusion barrier 102, and/or current spreading layer 210 can be formed of one or more ZnO-based alloys having a higher bandgap than the ZnO-based material in the active layer (e.g., quantum wells in the active layer). Optionally, substrate 240 can be formed of one or more ZnO-based materials (e.g., ZnO or ZnO alloys) having a higher bandgap than the ZnO-based material in the active layer (e.g., quantum wells in the active layer).

[0051] ZnO-based materials can include an oxide containing Zn, examples of which include oxides of Group HA and/or Group HB with Zn, in addition to ZnO itself. Specific examples of ZnO-based materials include ZnO, ZnMgO, ZnCaO, ZnBeO, ZnSrO, ZnBaO, ZnCdO, and alloys of these materials, such as MgCdZnO. Each of the above materials can be optionally alloyed with a Group VI element, such as Group VIA elements (e.g., Te, Se, and/or S) and/or Group VIB elements (e.g., Cr, Mo, W).

[0052] In some embodiments, a ZnO-based material can include alloying elements such as Group II elements (e.g., Mg, Be, Ca, Sr, Ba, Cd, or other related elements), Group VI elements (e.g., Te, Se, S, or other related elements) or combinations thereof. The alloying elements can enable the formation of a ternary or quaternary compound that can allow for greater flexibility in engineering the bandgap and/or lattice parameter(s) of the ZnO-based material, which can be useful in device structures that employ stacked semiconductor epitaxial layers having differing bandgaps. [0053] In some embodiments, alloying with an element on the oxygen sub-lattice can vary (e.g., decrease and/or increase) the bandgap of a ZnO-based material. Such alloying is described in PCT publication WO/2008/073469, filed December 11, 2007 entitled "Zinc Oxide Multi- Junction Photovoltaic Cells and Optoelectronic Devices," commonly owned by the assignee and herein incorporated by reference in its entirety. Alloying with an element on the oxygen sub-lattice can further vary (e.g., decrease or increase) the bandgap of the ZnO-based material beyond what can be achieved using only alloying with an element on the zinc sub-lattice (e.g., as a result of the solubility limit of the zinc sub-lattice element in ZnO).

[0054] A ZnO-based material can be a p-type conductivity semiconductor, an n- type conductivity semiconductor, or an intrinsic conductivity semiconductor. P-type dopants can be included in the ZnO-based material, including one or more suitable Group IA, IB, VA and/or VB elements, such as K, Au, Ag, N, P As, Sb and/or other appropriate elements. N-type dopants can be included in the ZnO-based material, including one or more suitable Group III elements (e.g., B, Al, Ga, In, and/or Tl) and/or Group VII elements (e.g., F, Cl, Br, I). Co-doped semiconductors (e.g., a ZnO- based semiconductor, a Group-Ill nitride semiconductor) can include both n-type and p-type dopants.

[0055] In some embodiments, the semiconductor device layers can have an hexagonal crystal structure (e.g., a wurtzite crystal structure), examples of which can include ZnO-based semiconductors or Group III -nitride semiconductors. First conductivity type layer 108, active layer 104, and second conductivity type layer 106 can be epitaxially deposited on a substrate 240 that can also have a hexagonal crystal structure (e.g., a wurtzite crystal structure). By providing a substrate 240 formed of a semiconductor having an hexagonal crystal structure (e.g., a wurtzite crystal structure such as ZnO-based single crystal substrate or III-N single crystal substrate) that is cut and polished along a desired crystal plane (e.g., non-polar planes, semi-polar planes, or polar planes), deposited layers having layer interfaces that are parallel to the desired crystal plane can be formed on the substrate.

[0056] In some embodiments, the deposited layers can form layer interfaces that are oriented substantially parallel to a non-polar plane, or vicinal plane thereof, of the crystal structure (e.g., m-plane or a-plane of an wurtzite crystal structure). In other embodiments, the deposited layers form interfaces that are oriented substantially parallel to a semi-polar plane, or vicinal plane thereof, of the crystal structure. In yet other embodiments, the deposited layers form interfaces that are oriented substantially parallel to a polar plane of the crystal structure (e.g., c-plane of the wurtzite crystal structure). Such epitaxial deposition processes are described in PCT publication WO/2009/143226, filed May 20, 2009 entitled "Zinc-Oxide Based Epitaxial Layers and Devices," commonly owned by the assignee and herein incorporated by reference in its entirety.

[0057] In some embodiments, the active layer (e.g., including at least one quantum well layer) has an wurtzite crystal structure and has layer interfaces oriented substantially parallel to a non-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure, for example an m-plane or a-plane, or a vicinal plane thereof. In other embodiments, the active layer (e.g., at least one quantum well layer) has a wurtzite crystal structure and has layer interfaces oriented substantially parallel to a semi-polar plane, or a vicinal plane thereof, of the wurtzite crystal structure. In either case, dopant diffusion barriers can be desirable, since dopant diffusion along directions normal to non-polar (e.g., m-plane, a-plane) or semi-polar planes can be greater than along directions normal to polar planes (e.g., c-plane) of the wurtzite crystal structure.

[0058] Diffusion of dopants along non-polar and semi-polar plane normal directions of a ZnO-based semiconductor can be much higher than diffusion of those dopants along polar plane normal directions. In particular, the diffusion of p-type ZnO dopants, such as Ag, can be substantially faster along non-polar plane normal directions (e.g., m-plane normal, a-plane normal) than along polar plane normal directions (c-plane). Layers having one or more of these characteristics will especially benefit from the diffusion barrier layer described herein. For example, when deposited semiconductor layers are substantially parallel to non-polar (e.g., m-plane, a-plane) or semi-polar planes and the first conductivity type semiconductor layer 108 is a p-type ZnO-based semiconductor layer doped with a p-type dopant (e.g., Group IA, IB, or V dopants), a dopant diffusion barrier 102 is used to inhibit the diffusion of the p-type dopant from semiconductor layer 108 and into the active layer 104. Such a diffusion barrier can also be useful to impede any diffusion that can be present when layers are substantially parallel to polar planes (e.g., c-plane). [0059] In some embodiments, dopant diffusion barrier 102 includes one or more strained semiconductor layers. Dopant diffusion barrier 102 can include one or more compressively strained semiconductor layers and/or one or more tensilely strained semiconductor layers. Strain can be introduced into a layer in many ways according to methods appreciated by one of skill in the art. For example, strained semiconductor layers can be formed of semiconductor layers that are thin enough to inhibit complete relaxation of the layer. For example, a strained semiconductor layer can be thinner than a critical thickness associated with the strain level of the semiconductor material that forms the layer. Critical thickness varies with lattice mismatch and can range anywhere from a few nanometers for high lattice mismatch to thousands of nanometers for very low lattice mismatch. For alloyed and unalloyed ZnO layers, typical critical thickness is in the range of about 5 nm to about 500 nm, depending on the lattice mismatch and elastic properties of the materials.

[0060] The strain level of a deposited semiconductor layer can be described by the in-plane lattice mismatch between the deposited semiconductor layer and an underlying semiconductor layer upon which that deposited semiconductor layer is formed. The deposited semiconductor layer can be partially or completely strained, as can be described by an in-plane strain level. The in-plane strain level (ε//) of the deposited semiconductor layer is the difference between the strained in-plane lattice constant (a// _stra med) of the deposited semiconductor layer and a relaxed in-plane lattice constant (a// _re i _a χed) of the deposited semiconductor layer, divided by the relaxed in- plane lattice constant of the semiconductor layer: ε// = (a// _stram ed - a// _re iaxed)/a// _r eiaxed- For deposited layers thinner than their critical thickness, the deposited layer is fully strained and has the same in-plane lattice constant as the underlying layer on which it is deposited. In such a case, the strained in-plane lattice constant of the deposited layer equals the in-plane lattice constant of the underlying layer, and thus the in-plane strain level (ε//) of the deposited semiconductor layer is given by in-plane lattice mismatch between the layers.

[0061] Strain arises from the layer on which the dopant diffusion barrier is deposited. If deposition is performed over the second layer, then that is what will determine the strain. However, in the LED configuration, the first layer and the second layer are the cladding layers and both have the same alloy level and lattice constant, so the strain value is the same irrespective of which lattice constant one uses to calculate the lattice mismatch. Furthermore, one can grow the structure in reverse in some embodiments.

[0062] In some embodiments, the in-plane strain level of dopant diffusion barrier 102 is at least about 0.1%. In other embodiments, the in-plane strain level of dopant diffusion barrier 102 is at least about 0.2%. In yet other embodiments, the in-plane strain level of dopant diffusion barrier 102 is at least about 0.4%. In yet other embodiments, the in-plane strain level of dopant diffusion barrier 102 is at least about 1%. In some embodiments, the in-plane strain of the dopant diffusion barrier is compressive. In some embodiments, the in-plane strain of the dopant diffusion barrier is tensile. The type of strain, namely compressive or tensile strain, desired to inhibit dopant diffusion can depend on the diffusion mechanism of the dopant. For example, the inventors have appreciated that in the case of a Group IA p-type dopant of Ag in ZnO-based materials, compressive strain can inhibit diffusion of Ag. Specifically, in- plane compressive strains of greater than about 0.4% can substantially inhibit diffusion of Ag in directions normal to the plane, however lower strain levels can also impede diffusion of Ag.

[0063] In some embodiments, dopant diffusion barrier 102 can include one or more layers (e.g., strained layers) of metal oxides, ZnO, ZnO-alloys, and/or III -N compound semiconductors. Regarding ZnO-based compound semiconductors, one or more layers (e.g., strained layers) can be formed of ZnO-alloys including Group II (e.g., Group HA and/or HB) and/or Group VI (e.g., Group VIA and/or Group VIB) alloying elements. For example, a ZnO-alloy can be formed by alloying ZnO with any suitable Group II element such as Cd, Hg, Mg, Be, Ca, Sr, or other appropriate elements. A ZnO-alloy can also be formed by alloying ZnO with any suitable Group VI element such as S, Se, Te, Mo, Cr, W, or other appropriate elements. Such Group II and/or Group VI alloys of ZnO can be useful as the alloying elements are isovalent with either Zn or O and therefore can be readily p-doped, n-doped, or formed as intrinsic layers. Thus, such compound semiconductors can be readily incorporated into dopant diffusion barriers on either side of a p-n junction device without impeding the junction operation.

[0064] For example, a dopant diffusion barrier 102 can include one or more Zn^ JVIg _x O (e.g., 0<x<l, more preferably about 0.01<x<about 0.5) and/or Zni _-x Cdi _-x O (e.g., 0<x<l, more preferably about 0.01<x<about 0.5) semiconductor layers. Such layers can be strained via deposition on a relaxed ZnO layer. For example, a Zno 63Mgo 37O layer is believed to have an in-plane lattice mismatch of about 0.5% and a critical thickness of less than about 40 nm, specifically about 38 nm, for deposition onto the c-plane of a relaxed ZnO semiconductor layer. Such a layer with a thickness of less than about 40 nm (e.g., less than about 30 nm, less than about 20 nm, less than about 10 nm) can therefore form a compressively strained layer on a relaxed c-plane ZnO semiconductor layer. A thicker layer is desired to provide a larger barrier to dopant diffusion. The thickness of the strained layer preferably does not exceed the critical thickness of that layer, so as to not relax the layer. In the above example, of Zni _-x Mg _x O, the strained layer can have a thickness greater than about 20 nm (e.g., greater than about 25 nm, greater than about 30 nm) while at the same time not exceeding the critical thickness of the strained layer. Similar considerations apply to other strained layers, such as Zni _-x Cdi _-x O layers.

[0065] In some embodiments, a dopant diffusion barrier 102 can include one or more layers deposited over a relaxed layer (e.g., part or all of layer 106 of FIG. 2A), with or without intervening layers, where the relaxed layer has a lattice mismatch with an underlying deposition substrate. The relaxed layer can include an alloying element, and the dopant diffusion barrier 102 can include a layer having the alloying element in a greater concentration than the relaxed layer. In some embodiments, a dopant diffusion barrier 102 can include one or more Zni _-x Mg _x O and/or Zni _-x Cdi _-x O semiconductor layers formed over relaxed Zni _-y Mg _y O and/or Zni _-y Cdi _-y O semiconductor layers (e.g., corresponding to part or all of layer 106 in FIG. 2A), with or without intervening layers, where x>y with l>y>0 and l>x>0. For example, y=0 corresponds to deposition over relaxed ZnO, for example a ZnO substrate, as discussed above. Alternatively, y can be greater than 0. In some embodiments where y>0, the dopant diffusion barrier 102 can include one or more strained Zni _-x Mg _x O layers formed over a relaxed Zni _-y Mg _y O layer having y>0, with or without intervening layers. In some embodiments, y is greater than about 0.2 (e.g., greater than about 0.25, greater than about 0.3). In some of these embodiments, x is greater than about 0.25 (e.g., greater than about 0.3, greater than about 0.35).

[0066] In some embodiments, the relaxed layer over which the dopant diffusion barrier 102 is formed can include an alloying element, and the dopant diffusion barrier 102 can include a layer having the alloying element in a lower concentration than the relaxed layer. A dopant diffusion barrier 102 can include one or more Zni _-x Mg _x O and/or Zni _-x Cdi _-x O semiconductor layers formed over relaxed Zni _-y Mg _y O and/or Zni. yCdi.yO semiconductor layers, where x<y with l>x>0 and l>y>0. Such structures can be formed by deposition of relaxed Zni _-y Mg _y O and/or Zni _-y Cdi _-y O semiconductor layers having a thickness greater than their critical thickness prior to the deposition of the one or more Zni _-x Mg _x O and/or Zni _-x Cdi _-x O semiconductor layers. Such layers can be deposited on any suitable substrate, for example a ZnO substrate. When x<y, the Zni _-x Mg _x 0 and/or Zni _-x Cdi _-x O semiconductor layers can be made to have the opposite strain type (i.e., compressive or tensile) than when x>y. Such structures can be particularly useful when the strain type desired to impede a given dopant diffusion is opposite to that achieved via deposition onto a relaxed ZnO surface. In some embodiments, y is greater than about 0.25 (e.g., greater than about 0.3, greater than about 0.35). In some of these embodiments, x is less than about 0.2 (e.g., less than about 0.15, less than about 0.1). In some embodiments, x is 0.

[0067] Alternatively, in some embodiments, dopant diffusion barriers can include ZnO-alloys formed with alloying elements that are aliovalent with ZnO, and therefore can also alter the doping character of the diffusion barrier. Alloying ZnO with an aliovalent metal element can be used to form an effective dopant diffusion barrier. In some embodiments, a dopant diffusion barrier can include one more transition metals (e.g., Mn, Co, V, Nb, Hf, Ti, etc.) or other metal. For example, the dopant diffusion barrier can be a metal oxide where the metal includes a transition metal (e.g., Mn- oxide, Co-oxide, V-oxide, Nb-oxide, Hf-oxide, Ti-oxide), and can also be a ZnO-alloy including a transition metal. In some embodiments, the transition metal can have an ionic radius larger than the zinc ionic radius. Alternatively, the transition metal can have an ionic radius smaller than the ionic radius of zinc. The inventors have observed that depositing a Zni _-X A1 _X O layer (e.g., 0<x<l, more preferably about 0.01<x<about 0.5) on a relaxed ZnO substrate forms a compressive layer that inhibits the diffusion of ZnO p-type dopants, such as Group I dopants like Ag. However, such a diffusion barrier can be n-type as a result of Al presence in the layer, and as such can not be desired as a dopant diffusion barrier on a p-side of an active layer. It should however be appreciated that such diffusion barriers can be useful in other device configurations.

[0068] In some embodiments, the thickness of the dopant diffusion barrier 102 is less than the critical thickness for the strained layer deposited over the underlying layer. For example, the dopant diffusion barrier 102 can have a thickness less than about 100 nm (e.g., less than about 50 nm, less than about 25 nm, less than about 10 nm). Such a thin dopant diffusion barrier 102 can particularly compatible with the device structure as the dopant diffusion barrier will not substantially impact the desired energy band configuration for the electrical operation of the device. [0069] The dopant diffusion barrier can also serve a function in the electrical operation of the device. For example, in some embodiments, the dopant diffusion barrier 102 or at least a portion of the dopant diffusion barrier 102 can be configured to serve as a carrier blocking layer that can block the carriers (e.g., electrons and/or holes) from overflowing past the active layer 104 and into the cladding layers during device operation. That is, the layer serves as an impediment to both ionic (dopant cations) and electronic (carrier) flow. A carrier blocking layer can be created by selecting the appropriate band offsets (e.g., via alloy composition and/or strain engineering) to achieve the desired carrier blocking for the desired carriers (e.g., electrons and/or holes). For example, an electron blocking layer can be disposed between a p-cladding layer and the active layer, and can have a larger energy bandgap than the p-cladding layer, so as to mitigate the overflow of electrons from the active layer into the p-clad layer. In such an example, the electron blocking layer can also serve as the dopant diffusion barrier as the difference in allying content will provide sufficient lattice mismatch to introduce strain into the layer. In another example, the dopant diffusion barrier can be a gate dielectric of a transistor device, for example the gate dielectric of a field effect transistor. In yet another example, the dopant diffusion barrier can be a device contact layer that prevents dopants in a metal oxide transparent contact from diffusing into the device semiconductor layers.

[0070] In some embodiments, dopant diffusion barrier 102 can include a plurality of strained layers separated by spacer layers. The spacer layers can be strained or relaxed. The plurality of strained layers can be compressively strained and the spacer layers can be tensilely strained or relaxed. Alternatively, the plurality of strained layers can be tensilely strained and the spacer layers can be compressively strained or relaxed. Such a configuration can provide for the formation of dopant diffusion barriers having a superlattice structure.

[0071] In some embodiments, dopant diffusion barrier 102 can be a monocrystalline layer having a dislocation density of less than about 10 ⁶ cm ^"2 (e.g., less than about 10 ⁵ cm ^"2 , less than about 10 ⁴ cm ^"2 , less than about 10 ³ cm ^"2 , less than about 10 ² cm ^"2 ), as measured using etch pit density methods. Such a low dislocation density can be achievable as a result of the deposition of epitaxial layers having a composition that can be substantially lattice-matched to the substrate. The epitaxial layers can have a lattice mismatch with the substrate deposition surface of less than about 2.5% (e.g., less than about 2%, less than about 1%, less than about 0.5%, less than about 0.25%). For example, ZnO-based epitaxial layers, such as ZnO itself and/or ZnO-based alloys including Mg, Ca, Be, Sr, Ba, Cd, Se, Te, and/or S with a suitable atomic fraction, can be deposited on a ZnO substrate so as to achieve a low lattice mismatch with the substrate.

[0072] In some embodiments, at least a portion or all of dopant diffusion barrier 102 can be doped (e.g., doped with n-type and/or p-type dopants). For example, at least a portion of dopant diffusion barrier 102 can have the same conductivity type as first conductivity type semiconductor layer 108. This can be achieved by doping dopant diffusion barrier 102 with the first conductivity type dopant. In other embodiments, at least a portion or all of dopant diffusion barrier 102 can be undoped so as to form an intrinsic portion.

[0073] During operation of a light-emitting device, such as the device 200 of FIG. 2A, electrical power can be injected to active layer 104 via electrodes 220 and 230. Electrons and holes can recombine radiatively at active layer 104 thereby generating light. Light generated in the active layer can be emitted towards the top emission surface or reflective layer 260. Light impinging on the top emission surface can be extracted at least partially, and some of the impinging light can be reflected back. Reflective layer 260 can reflect the light back toward the top emission surface. The light can undergo multiple passes before light extraction is complete. During device operation, dopant diffusion barrier 102 can impede the diffusion (e.g., electromigration-mediated diffusion) of first conductivity type dopant of semiconductor layer 108 into the active layer.

[0074] The device 200 of FIG. 2A can be fabricated by depositing layers 106, 104, 102, 108, and 210 on substrate 240. The deposition process can include using conventional techniques such as chemical deposition techniques (e.g., MOCVD, plasma CVD) and/or physical deposition techniques (e.g., MBE). In a preferred embodiment, layers 106, 104, 102, 108, and 210 are deposited in a single deposition process, such as an MOCVD or MBE process. Alternatively, when present, current spreading layer 210 can be deposited separately in another deposition system (e.g., using chemical or physical deposition processes) after the deposition of semiconductor layers 106, 104, 102, and 108.

[0075] In one or more embodiments, ZnO-based materials can be formed as a crystalline thin film on a substrate, such as an epilayer deposited on a substrate. Epitaxial layers of ZnO-based materials can be deposited onto various substrates such as ZnO-based substrates, MgO, Ill-nitride (e.g., GaN, AlN), sapphire, SiC, silicon, or ScAlMg substrates. In some embodiments, the substrate can be a single crystal substrate. In other embodiments, the substrate can be polycrystalline or noncrystalline (e.g., glass or plastic substrates).

[0076] A ZnO-based epilayer can be deposited using conventional techniques such as chemical deposition techniques (e.g., MOCVD, plasma CVD), physical deposition techniques (e.g., MBE, pulsed laser deposition, plasma assisted PLD) and the like. The ZnO-based material, in the form of an epilayer or otherwise, can be p- doped, n-doped, undoped, or compensated.

[0077] U.S. Patent Application 11/551058, filed on October 19, 2006 entitled "Zinc Oxide Based II-VI Compound Semiconductor Layers with Shallow Acceptor Conductivities and Methods of Forming Same," which is hereby incorporated in its entirety by reference, discloses chemical vapor deposition fabrication techniques that enable the use of ZnO compounds in various applications. The fabrication techniques overcome difficulties relating to reliably fabricating p-type ZnO materials with sufficiently high concentrations of relatively shallow acceptor impurities operating as p-type dopants. The same methods used for p-type doping can also be used to prepare n-type ZnO by selection of the appropriate n-type dopants. An n-type ZnO can be prepared by using dopants including Al, Ga and In, or other appropriate elements. By way of example, ZnO can be doped with In at concentrations ranging from approximately IxIO ¹² to IxIO ²⁰ cm ^"3 . The same fabrication techniques can be used to prepare n-type, p-type, undoped, and/or compensated ZnO alloys. In some embodiments, epitaxial layers of ZnO-based materials can be doped with p-type species such as Ag, Au and K and which can have as much as about 50% acceptor activation in ZnO. In a similar manner, epitaxial layers of ZnO-based materials can be doped with n-type species such as aluminum, gallium or indium. [0078] In some embodiments, the processing techniques for incorporating p-type dopants can include implanting the silver, potassium and/or gold dopants into the ZnO-based compound semiconductor layer at dose levels of greater than about IxIO ¹³ cm ^"2 and, for example, in a range from about IxIO ¹³ cm ^"2 to about IxIO ¹⁵ cm ^"2 . This implanting step can be performed as a single implanting step or as multiple implanting steps, which can be performed at multiple different implant energy levels to thereby yield multiple implant peaks within the layer. An annealing step can then performed to more evenly distribute and activate the dopants and repair crystal damage within the layer. This annealing step can include annealing the ZnO-based compound semiconductor layer at a temperature in a range from about 250 ⁰ C to about 2000 ⁰ C, in an ambient (e.g., chemically inert ambient) having a pressure in a range from about 25 mbar to about 7 kbar. In certain applications, it can be preferable to perform the annealing step at a temperature in a range from about 700 ⁰ C to about 700 ⁰ C, in an oxygen ambient environment having a pressure of about 1 atmosphere. Similar ion implantation and anneal processes can be used for n-type dopants. [0079] In some embodiments, a p-type ZnO-based compound semiconductor layer can be formed using an atomic layer deposition (ALD) technique, e.g. a deposition technique that includes exposing a substrate to a combination of gases. This combination can include a first reaction gas containing zinc at a concentration that is repeatedly transitioned (e.g. pulsed) between at least two concentration levels during a processing time interval, and a second reaction gas containing oxygen and a p-type dopant gas containing at least one p-type dopant species selected from a group consisting of silver, potassium, gold, or an n-type dopant gas, as appropriate. A concentration of oxygen in the second reaction gas can be repeatedly transitioned between at least two concentration levels. In particular a concentration of zinc in the first reaction gas and a concentration of oxygen in the second reaction gas can be transitioned in an alternating sequence so that relatively high zinc concentrations in the first reaction gas overlap with relatively low oxygen concentrations in the second reaction gas and vice versa.

[0080] Methods of forming a p-type ZnO-based compound semiconductor layer can also include using an iterative nucleation and growth technique. This technique can include using an alternating sequence of deposition/growth steps that favor c- plane growth (i.e., vertical growth direction, which causes nucleation) at relatively low temperatures interleaved with a-plane growth (i.e., horizontal growth direction, which causes densification) at relatively high temperatures to coalesce the layer. Iterative nucleation and growth can include depositing a plurality of first ZnO-based compound semiconductor layers at a first temperature in a range from about 200 ⁰ C to about 600 ⁰ C and depositing a plurality of second ZnO-based compound semiconductor layers at a second higher temperature in a range from about 400 ⁰ C to about 900 ⁰ C. These first and second ZnO-based compound semiconductor layers are deposited in an alternating sequence so that a composite layer is formed. [0081] Still other methods of forming a p-type ZnO-based compound semiconductor layer include exposing the substrate to a combination of a first reaction gas containing zinc, a second reaction gas containing oxygen and a p-type dopant gas containing at least one p-type dopant species selected from a group consisting of silver, potassium and gold, while simultaneously trans itioning a temperature of the substrate between at least two temperatures. These two temperatures can include a first lower temperature in a range from about 200 ⁰ C to about 600 ⁰ C and a second higher temperature in a range from about 400 ⁰ C to about 900 ⁰ C. [0082] According to aspects of these embodiments, the concentration of the p-type dopant species in the p-type dopant gas is repeatedly transitioned between two concentration levels while the temperature of the substrate is also being transitioned between the two temperatures. In particular, the concentration of the p-type dopant species in the p-type dopant gas is transitioned in an alternating sequence relative to the trans itioning of the temperature of the substrate so that relatively high concentrations of the p-type dopant species in the p-type dopant gas overlap with relatively low temperatures of the substrate and vice versa. Alternatively, the concentration of the p-type dopant species in the p-type dopant gas is transitioned so that relatively high temperatures of the substrate overlap with a timing of relatively high concentrations of the p-type dopant species in the p-type dopant gas. [0083] In some embodiments, one or more ZnO-based compound semiconductor layer(s) can be formed on a substrate using a chemical vapor transport technique (e.g., MOCVD). This technique can include transporting concentrations of a plurality of reaction gases in a carrier gas towards a substrate that is exposed to an ambient at growth temperature(s) between about 300 ⁰ C and about 1000 ⁰ C. The pressure of the ambient is held in a range from about 20 Torr to about 76 Torr. By varying the reaction gases and/or their flow rates, one or more semiconductor layers (e.g., monocrystalline semiconductor layers) having desired compositions can be deposited on the substrate. Controlling the reaction can be used to control the thickness of each semiconductor layer. Reaction gases can include diethylzinc for Zn, and oxygen gas for O. Alternative oxygen reaction gases can include carbon dioxide, nitrous oxide, and/or nitrogen dioxide. Other reaction gases can be used for additional elements present in the desired semiconductor layer, such as cyclopentadiethylmagnesium for Mg, diethylcadmium for Cd, di-tertiary-butylselenium for Se, and other reaction gases known to those of ordinary skill in the art. Other reaction gases that can be employed can include ethyl chloride as an n-type dopant gas of Cl, plasma N ₂ or the like as a p- type dopant gas, or any other reaction gases known in the art for providing the desired elements for deposition.

[0084] In some embodiments, a condensed matter source can be used for some doping and/or alloying elements (e.g., Ag, Au, K) to circumvent limited availability of some volatile species using conventional metalorganic transport temperatures (e.g., < 30 ⁰ C) and equipment. When using a condensed matter source, the source can be converted to a gas prior to transport. A condensed matter source can include a source in a solid phase, a liquid phase or a semisolid phase, such as a gel. A bubbler or heater containing the condensed matter source can be heated to above room temperature in order to convert the source to the gas phase.

[0085] The condensed matter source can, preferably, include non-halogenated and non-silylated complexes, or can include halogenated or silylated complexes. When using non-halogenated or non-silylated complexes, the material should have sufficient vapor pressure at reasonable elevated temperatures. For example, non-halogenated or non-silylated solid sources of Ag, Au and K can have a vapor pressure ranging from about 10 ^~5 to about 10 ³ torr between about 30 ⁰ C and about 200 ⁰ C. Generally, the sublimation of Au and K occurs at higher temperatures relative to Ag sublimation because of much lower volatility of their ligands.

[0086] Examples of some non-halogenated and non-silylated precursors that can be used for the source are listed below in Table 1 and some halogenated or silylated precursors that can be used are listed below in Tables 2 and 3, although others can be used.

Table 1 : Non-halogenated and non-silylated precursors of Ag, Au and K

Table 2: List of Halogenated or Silylated Silver and Gold Precursors

Table 3: List of Halogenated or Silylated Potassium Precursors

[0087] For example, when using silver atoms for the p-type dopant and/or an alloying element, the vapor pressure of the silver-based condensed matter source or precursor can typically be between at least about 10 ^~5 to about 10 ³ torr. The conversion of the silver-based precursors can be achieved by heating the bubbler or heater that contains one or more selected compounds (e.g., compounds containing Ag, Au, or K) to at or above the compound's sublimation temperature, but below its decomposition temperature. For example, for some silver-based compounds, the sublimation temperature can be between about 30 ⁰ C to about 205 ⁰ C and the decomposition temperature can be between about 80 ⁰ C to about 300 ⁰ C. For instance, when using silver trifiuoroacetate (CF ₃ COOAg) as the precursor, the heater can be uniformly heated to an elevated temperature of about 60 ⁰ C (or higher) to ensure that significant vapor pressure of the precursor (e.g., ≥about 10 ^"5 torr) is achieved even though the actual sublimation temperature Of CF ₃ COOAg commences at around about 30 ⁰ C in air. Similarly, when using silver trialkyphosphine- acetylacetonate (AcAcAgP ₃ ) as the precursor, the heater can be heated to a temperature of about 180 ⁰ C (or higher) to ensure that significant vapor pressure of the precursor (e.g., ≥IO ^"1 torr) is achieved even though the actual sublimation temperature OfAcAcAgP ₃ commences at around about 80 ⁰ C in air. As known to those skilled in the art, the sublimation temperatures can be marginally different in a vacuum. [0088] To form a ZnO-based material layer, a reaction gas comprising zinc can be provided from a zinc-based source, a reaction gas comprising oxygen can be provided from an oxygen-based source, and other one or more other reactions gases supplying other elements (e.g., alloying and/or doping elements) desired in the ZnO-based material. The zinc-based source and the oxygen-based source are typically supplied in the gas phase, although the source can be in a solid, liquid, or semisolid phase. [0089] Reaction gases including alloying and/or dopant atoms can be transported to one or more substrates located within a reactor chamber. As known to those skilled in the art, the substrate can be a wafer processed in a variety of ways and can include a variety of materials. For ZnO-based films, the substrate preferably is a ZnO substrate (e.g., a single crystal ZnO substrate), although other materials can be used, as previously described.

[0090] Transport of gas species converted from condensed matter sources can be achieved by heating gas lines to an elevated temperature in order to limit or prevent condensation of the converted species during transport prior to delivery into a reactor chamber. The elevated temperature should be at least the minimum temperature of actual conversion/sublimation (e.g., about 30 ⁰ C in the case Of CF ₃ COOAg, about 80 ⁰ C in the case OfAcAcAgP ₃ ) and preferably higher. For example, the elevated temperature gas lines can be maintained at approximately the same temperature as the bubbler (e.g., about 60 ⁰ C in the case Of CF ₃ COOAg, about 180 ⁰ C in the case of AcAcAgP ₃ ) or higher. For instance, the heated gas lines can be maintained at about 190 ⁰ C in the case OfAcAcAgP ₃ .

[0091] An inert gas, such as argon, can be supplied into the heated bubbler through an inlet port via gas lines and allowed to exit through an outlet port into the heated gas lines. The inert gas can or can not be heated to an elevated temperature in gas lines prior to entering the heater. The elevated temperature gas transport lines can have valves and gauges that utilize special seals (e.g., such as polyimide and stainless steel), which can enable the flow regulation of the transported species within the temperature range of interest. Gas lines transport the second gas and the third gas, respectively, to the reactor chamber. The elevated temperature gas lines can be separate from the gas lines used from transporting the reaction gases of other elements (e.g., Zn and O ₂ ) to prevent any premature reactions.

[0092] As is known by those skilled in the art, the deposition process can be conducted in the reactor chamber where the reaction gases can be combined. One or more additional gases can also be used, such as multiple organometallic precursors, reaction gases, inert carrier gases, etc.

[0093] Control of the process gas composition can be accomplished using mass- flow controllers, valves, etc., as known by those skilled in the art. The one or more substrates are typically heated to an elevated temperature in the reactor chamber. As the gases enter into the reactor, pyro lysis of the precursor complexes occurs either in the gas mixture or at the surface of the substrate when the gas mixture contacts the heated substrate surface. In some embodiments, such an MOCVD process can be used to deposit a ZnO-based semiconductor layer including Ag and/or Au with an atomic fraction greater than about 0.01 on one or more substrates. [0094] In other embodiments, a ZnO-based compound semiconductor layer can be formed on a substrate using a molecular beam epitaxy technique. Using this technique, the desired elements to form the ZnO-based layer can be evaporated from one or more Knudsen cells to a substrate in a partial pressure of oxygen. For example, in the case of a ZnO-based material including Ag and/or Au elements (e.g., for doping and/or alloying), the Ag and/or Au can be evaporated from a first Knudsen cell concurrently with the evaporation of Zn from a second Knudsen cell in a partial pressure of oxygen. Additional Knudsen cell(s) can evaporate one or more other elements (e.g., Mg, Be, Ca, Sr, Ba, Cd, Te, Se, S, In, Al, Ga, or other elements) so as to form any desired ZnO-based material on the substrate. The temperature of the substrate is typically held at a temperature of greater than about 300 ⁰ C and at pressures ranging from about 25 mbar to about 700 mbar.

[0095] Still further embodiments can include using a physical vapor transport technique that includes transport of zinc to a substrate by evaporation, magnetron sputtering, flame hydrolysis deposition or sublimation. Alternatively, liquid phase epitaxy techniques and solvus-thermal incorporation techniques can also be used to form the ZnO-based compound semiconductor.

[0096] The above-mentioned techniques can be employed to produce structures and devices that employ n-type, p-type, undoped, and/or compensated ZnO-based materials (e.g., ZnO-based epilayers). These techniques use processing conditions that can yield a net p-type dopant concentration of greater than about IxIO ¹⁷ cm ^"3 therein, for dopants having an acceptor ionization energy below about 355 meV. The processing conditions can also yield a dopant activation level of greater than about 10% for the dopants having the desired acceptor ionization energy. [0097] Returning to the fabrication processes for the devices illustrated in FIGs. 2A and 2B, after deposition of layers 106, 104, 102, 108, and 210 onto substrate 240, a masked etch (e.g., dry etching and/or wet etching) of the semiconductor surface can be performed so as to expose a contact layer of semiconductor layer 106 (e.g., semiconductor layer 262 shown in the device 202 of FIG. 2B) in a portion of each chip. Electrode 220 can be formed on the etched surface of semiconductor layer 106 using metal deposition (e.g., evaporated and/or sputtered) and a liftoff process employing a patterned mask. Similarly, metal layer(s) that form electrode 230 can be deposited (e.g., evaporated and/or sputtered) on a patterned mask disposed on current spreading layer 10. A lift-off process can also be used to then form electrode 230 by selectively removing the mask. Electrodes can cover an area of about 50 μm ² to about 400 μm ² , with a preferred area being about 100x100 μm ² . A reflective layer 260, such as a metal layer including Ag and/or Al, can be deposited (e.g., evaporated, sputtered) on the backside of substrate 240. A wafer including multiple die regions can be diced so as to form the die (chip) shown in the cross-section of FIG. 2A. [0098] Various modifications to the above processes and device structure are possible, such as a modification to the contacting geometry, for example using a vertical contacting geometry, such as is possible when using an electrically conductive substrate. [0099] FIG. 3 illustrates a cross-sectional view of another light-emitting device 300 including a dopant diffusion barrier, such as an LED or a laser diode. The device is similar to that of FIG. 2A, except that the device 300 can further include a second dopant diffusion barrier 310 disposed between second conductivity type layer 106 and active layer 4. Second dopant diffusion barrier 310 can inhibit the diffusion of the second dopant, thereby impeding the diffusion of the second dopant in second conductivity type layer 106 into the active layer 4. For example, if semiconductor layer 108 is p-doped and semiconductor layer 106 is n-doped, dopant diffusion barrier 310 can impede the diffusion of the n-dopant from semiconductor layer 106 into active layer 104.

[0100] In some embodiments, at least a portion of the second dopant diffusion barrier has the same conductivity type as the second conductivity type semiconductor layer 106, for example at least a portion of the second dopant diffusion barrier can be doped with the second conductivity type dopant. Alternatively, dopant diffusion barrier 310 can be an intrinsic layer. Dopant diffusion barrier 310 can have a similar structure a dopant diffusion barrier 102. For example, dopant diffusion barrier 310 can be formed of one or more strained semiconductor layers, as described previously in the context of dopant diffusion barrier 102. Furthermore, dopant diffusion barrier 310 can also serve other device functions, for example the dopant diffusion barrier can also serve as a hole blocking layer.

[0101] Although many of the structures and methods provided herein are described in the context of light-emitting devices (e.g., LEDs, LDs), these structure and methods can be applied to other devices, such as other opto-electronic, photonic, and electronic devices. Such devices can include photovoltaics, transistors (e.g., FETs, HBTs), photo-detectors, excitonic devices and integrated circuits (e.g., optical switches).

[0102] As used herein, when a structure (e.g., layer, region) is referred to as being "on", "over" "overlying" or "supported by" another structure, it can be directly on the structure, or an intervening structure (e.g., layer, region) also can be present. A structure that is "directly on" or "in contact with" another structure means that no intervening structure is present. A structure that is "directly under" another structure means that no intervening structure is present.

[0103] Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only. [0104] What is claimed is: