SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD

Title:

SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD

Document Type and Number:

WIPO Patent Application WO/2021/124549

Kind Code:

A1

Abstract:

A purpose of the present invention is to provide a technology that can both suppress inactivation of a p-type GaN layer and suppress a punch-through current. This semiconductor element comprises: an active trench that reaches from a third gallium nitride layer to a first gallium nitride layer; a recess that is adjacent to the active trench with the third gallium nitride layer interposed therebetween, and is a recessed section reaching from the third gallium nitride layer to a second gallium nitride layer; and a dummy trench that reaches from a bottom surface of the recess to the first gallium nitride layer.

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Inventors:

HAYASHIDA TETSURO (JP)
IMAI AKIFUMI (JP)
NANJO TAKUMA (JP)
WATAHIKI TATSURO (JP)

Application Number:

PCT/JP2019/050098

Publication Date:

June 24, 2021

Filing Date:

December 20, 2019

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP (JP)

International Classes:

H01L29/78; H01L21/336; H01L29/12

Foreign References:

JP2014183146A	2014-09-29
JP2019175905A	2019-10-10
JP2015079894A	2015-04-23
JPH05183189A	1993-07-23
JP2014116483A	2014-06-26

Attorney, Agent or Firm:

YOSHITAKE Hidetoshi et al. (JP)

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