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Title:
SEMICONDUCTOR INSPECTION DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2004/017082
Kind Code:
A1
Abstract:
A semiconductor inspection device includes: sampling means having n-1 delay sections for delaying a sampling clock of a clock generator, n digital converters for converting a response waveform output from a semiconductor device into digital data according to the sampling clock output from the clock generator and sampling clocks output from the n-1 delay sections, a storage section for storing sampling data output from the n digital converters, and a waveform combining section for combining the sampling data stored in the storage section to generate a digital sampling waveform; and data processing means for generating from the digital sampling waveform obtained from the waveform combining section, a frequency spectrum in which a noise component generated by skew in the n-1 delay sections has been corrected. A semiconductor device manufacturing method using the semiconductor inspection device is also disclosed.

Inventors:
LI WEN (JP)
MAKUUCHI MASAMI (JP)
TAKAHASHI MASAYOSHI (JP)
KIKUCHI SHUJI (JP)
Application Number:
PCT/JP2003/009951
Publication Date:
February 26, 2004
Filing Date:
August 05, 2003
Export Citation:
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Assignee:
HITACHI LTD (JP)
LI WEN (JP)
MAKUUCHI MASAMI (JP)
TAKAHASHI MASAYOSHI (JP)
KIKUCHI SHUJI (JP)
International Classes:
G01R23/16; G01R31/28; G01R31/316; G01R31/319; H01L21/66; H01L21/822; H01L27/04; H03M1/08; (IPC1-7): G01R31/316
Domestic Patent References:
WO2002059632A12002-08-01
Foreign References:
JPH07254855A1995-10-03
JP2001184602A2001-07-06
Attorney, Agent or Firm:
Ogawa, Katsuo (Yusenkayabacho Building 9-8, Nihonbashi-kayabacho, 2-chom, Chuo-ku Tokyo, JP)
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