Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2017/119316
Kind Code:
A1
Abstract:
The present technique relates to: a semiconductor integrated circuit capable of operating at a low voltage such that the destruction of a protective circuit can be prevented; and a control method therefor.
The semiconductor integrated circuit comprises: a resistive element and a capacitive element connected in series between a power source wiring and a ground wiring; an inverter whereof the input is connected between the resistive element and the capacitive element; an MOS transistor whereof the gate electrode receives the output from the inverter, and whereof the drain electrode and the source electrode are connected to the power source wiring and the ground wiring; and a current-limiting element inserted between the gate electrode and a well region where the MOS transistor is formed. The present configuration is applicable, for instance, in protective circuits wherein destruction of the internal circuit due to ESD is prevented.
Inventors:
FUKASAKU KATSUHIKO (JP)
NAKAGAWA DAISUKE (JP)
NAKAGAWA DAISUKE (JP)
Application Number:
PCT/JP2016/088377
Publication Date:
July 13, 2017
Filing Date:
December 22, 2016
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H01L21/822; H01L27/04; H01L27/06; H03K19/003
Foreign References:
| JP2013055102A | 2013-03-21 | |||
| JP2009231312A | 2009-10-08 | |||
| JP2006121007A | 2006-05-11 | |||
| JP2014229624A | 2014-12-08 | |||
| US20100140712A1 | 2010-06-10 | |||
| US20050013073A1 | 2005-01-20 |
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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