Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/083893
Kind Code:
A1
Abstract:
The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two delay times different from each other and outputs resultant signals as first and second delayed signals. A holding unit holds the first and second delayed signals in synchronization with a timing signal indicating a predetermined capture timing. A setup time detection unit detects whether or not one of the first and second delayed signals held within a setup time-side detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection unit detects whether or not the other of the first and second delayed signals held within a hold time-side detection period from the predetermined capture timing to a predetermined end timing has changed.

Inventors:
KAWAGUCHI YUYA (JP)
KUMANO KAZUO (JP)
Application Number:
PCT/JP2017/033413
Publication Date:
May 11, 2018
Filing Date:
September 15, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SONY CORP (JP)
International Classes:
H03K19/003; H03K5/26; H03K19/096
Foreign References:
JP2007108172A2007-04-26
US20150042375A12015-02-12
US20030223278A12003-12-04
JP2016025275A2016-02-08
JP2013062572A2013-04-04
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
Download PDF: