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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS PRODUCTION METHOD
Document Type and Number:
WIPO Patent Application WO/2004/073071
Kind Code:
A1
Abstract:
Chipping in the step of cleaning a high-melting metal film constituting a poly-metal gate is prevented, the characteristics of a device are improved, and the cleaning efficiency is improved. A low-resistance polycrystalline silicon film (9a), a WN film (9b), and a W film (9c) all provided over a substrate (1) are dry-etched using a silicon nitride film (10) as the mask to form a gate electrode (9) composed of the films, a thin oxide film (9d) is formed by wet-hydrogen oxidation, nitrogenization is conducted by the ROPN method, and the W film (9c) exposed from the side wall of the gate electrode is made a WN film (9e). As a result, chipping of the W film (9a) is prevented even if the later cleaning steps, for example, (1) the resist film photolithography step, (2) the impurity implantation step, (3) the resist film removing step, and (4) the substrate surface cleaning step are repetitively conducted when an n--type semiconductor region (11) and a p--type semiconductor region (12) are formed. Further, a strong cleaning liquid such as a U cleaning liquid or a hydrofluoric acid cleaning liquid can be used as a cleaning liquid.

Inventors:
MORIYA SATOSHI (JP)
Application Number:
PCT/JP2003/001428
Publication Date:
August 26, 2004
Filing Date:
February 12, 2003
Export Citation:
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Assignee:
HITACHI LTD (JP)
MORIYA SATOSHI (JP)
International Classes:
H01L21/28; H01L21/8239; H01L21/8242; H01L21/8244; H01L21/8247; H01L27/108; H01L27/118; (IPC1-7): H01L29/78; H01L21/336; H01L29/423; H01L29/788; H01L29/792; H01L27/115; H01L21/8247
Foreign References:
US20010020707A12001-09-13
JP2000223439A2000-08-11
JPH11340343A1999-12-10
JPH09266178A1997-10-07
US6303483B12001-10-16
US6171981B12001-01-09
JPH1050827A1998-02-20
JPH11186548A1999-07-09
Attorney, Agent or Firm:
Tsutsui, Yamato (3F AZERIA Bldg. 1-1, Nishi-shinjuku 8-chom, Shinjuku-ku Tokyo, JP)
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