Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING SAME
Document Type and Number:
WIPO Patent Application WO/2010/143326
Kind Code:
A1
Abstract:
Provided is a semiconductor integrated circuit device which has: a semiconductor chip (100) having a plurality of input/output cells (105); a plurality of pads (101, 102) formed on the surface of the semiconductor chip; and wiring lines (103, 104) formed between the pads on the surface of the semiconductor chip, said wiring lines electrically connecting at least some of the input/output cells (105) with at least some of the pads (101, 102). The pads (101, 102) are arranged in a quadrangular grid shape at the center portion of the semiconductor chip, and are arranged in a staggered manner at least on one corner portion of the four corner portions of the semiconductor chip.
Inventors:
YOKOYAMA KENJI
Application Number:
PCT/JP2010/000442
Publication Date:
December 16, 2010
Filing Date:
January 27, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
YOKOYAMA KENJI
YOKOYAMA KENJI
International Classes:
H01L21/3205; H01L21/822; H01L21/60; H01L21/82; H01L23/12; H01L23/52; H01L27/04
Foreign References:
| JP2002190526A | 2002-07-05 | |||
| JP2003007750A | 2003-01-10 | |||
| JP2005142281A | 2005-06-02 | |||
| JPH09172105A | 1997-06-30 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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