Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TERMINAL CONSTRUCTION OF REFERENCE CELL
Document Type and Number:
WIPO Patent Application WO/2011/145242
Kind Code:
A1
Abstract:
Disclosed is a semiconductor integrated circuit device which includes first and second reference cells (10, 20) adjacently arranged in a first direction. A connection wiring (25) is arranged so as to extend in the first direction and to electrically connect an output terminal section (11) and an input terminal section (21) which extend in a second direction orthogonal to the first direction. Taking the region where the connection wiring (25) is connected as a point of reference, the output terminal section (11) extends in a first orientation in the second direction but does not extend in a second orientation which is the opposite of the first orientation. Taking the region where the connection wiring (25) is connected as the point of reference, the input terminal section (21) extends in the second orientation in the second direction but does not extend in the first orientation.
Inventors:
TAKAHATA ATSUSHI
UEHARA HIROYUKI
UEHARA HIROYUKI
Application Number:
PCT/JP2011/000981
Publication Date:
November 24, 2011
Filing Date:
February 22, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
TAKAHATA ATSUSHI
UEHARA HIROYUKI
TAKAHATA ATSUSHI
UEHARA HIROYUKI
International Classes:
H01L21/822; G03F1/00; G03F1/68; G03F1/70; H01L27/04
Foreign References:
| JP2005175001A | 2005-06-30 | |||
| JP2007123682A | 2007-05-17 | |||
| JP2007317814A | 2007-12-06 | |||
| JP2007033919A | 2007-02-08 | |||
| JP2009210984A | 2009-09-17 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims: