Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2008/035392
Kind Code:
A1
Abstract:
If the phase change element in a memory cell formed at the intersection of, for
example, a word line (WL0) and a bit line (BL0) is to be reset so as to drive the phase
change element into an amorphous state, it is arranged that the rise and fall times
(trb,tfb) of the bit line (BL0) be longer than the rise and fall times (trw,tfw)
of the word line (WL0). The quenching of the phase change element required for
that resetting is performed by use of the fall time (tfw) of the word line (WL0).
In this way, a disturb current (IBL01) for the phase change element in an unselected
memory cell formed at the intersection of the bit line (BL0) and a word line (WL1)
can be reduced, thereby improving the reliability of the phase change memory.
Inventors:
KUROTSUCHI KENZO (JP)
HANZAWA SATORU (JP)
TAKAURA NORIKATSU (JP)
MATSUI YUICHI (JP)
HANZAWA SATORU (JP)
TAKAURA NORIKATSU (JP)
MATSUI YUICHI (JP)
Application Number:
PCT/JP2006/318481
Publication Date:
March 27, 2008
Filing Date:
September 19, 2006
Export Citation:
Assignee:
RENESAS TECH CORP (JP)
KUROTSUCHI KENZO (JP)
HANZAWA SATORU (JP)
TAKAURA NORIKATSU (JP)
MATSUI YUICHI (JP)
KUROTSUCHI KENZO (JP)
HANZAWA SATORU (JP)
TAKAURA NORIKATSU (JP)
MATSUI YUICHI (JP)
International Classes:
G11C13/00; H01L27/105
Domestic Patent References:
| WO2005112118A1 | 2005-11-24 |
Foreign References:
| JP2005108395A | 2005-04-21 | |||
| JP2006244561A | 2006-09-14 | |||
| JP2005267837A | 2005-09-29 | |||
| JP2004171625A | 2004-06-17 |
Attorney, Agent or Firm:
TSUTSUI, Yamato (6th Floor Kokusai Chusei Kaikan, 14, Gobancho, Chiyoda-k, Tokyo 76, JP)
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