SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

WIPO Patent Application WO/2014/041921

Kind Code:

A1

Abstract:

MV-PMOS (20) and MV-NMOS (30) constituting a high-side driver circuit are formed in an n partition region (2) formed on a p-type semiconductor substrate (1). MV-NMOS (30) is formed in a p-type partition region (3) of the midpoint potential (Vs) within the n-type partition region (2). An n-type epitaxial region (12) is formed outside the n-type partition region (2) of the surface layer of the p-type semiconductor substrate (1), and a pGND region (41) of a ground potential (GND) is formed on the exterior of the n-type epitaxial region (12). Between the p-type semiconductor substrate (1) and the n-type epitaxial region (12), there is provided a cavity (11) between the high-side driver circuit and the pGND region (41), and a p-type diffusion region (13) that reaches the cavity (11) through the n-type epitaxial region (12) is also provided. The midpoint potential (Vs) is impressed on the p-type partition region (3). This allows the incidence of malfunctioning and damage to be avoided, and chip size to be reduced.

Inventors:

IMAI TOMOHIRO (JP)
YAMAJI MASAHARU (JP)

Application Number:

PCT/JP2013/071079

Publication Date:

March 20, 2014

Filing Date:

August 02, 2013

Export Citation:

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Assignee:

FUJI ELECTRIC CO LTD (JP)

International Classes:

H01L27/08; H01L21/336; H01L21/764; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/088; H01L27/092; H01L29/786

Foreign References:

JP2005191263A	2005-07-14
JP2007273993A	2007-10-18
JP2007036062A	2007-02-08