Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/171937
Kind Code:
A1
Abstract:
Provided is a semiconductor integrated circuit device that comprises a flip-flop circuit using vertical nanowire FET (VNW FET) and has a layout structure for minimizing area. A latch unit (30) of the flip-flop circuit comprises: a feedback node (nd1); a transistor (P5, N5) in which one node receives an input signal and the other node is connected to the feedback node (nd1); and a transistor (P7, N7) in which one node is connected to the feedback node (nd1). In a standard cell, the tops of the transistors (P5, N5, P7, N7) are connected to the feedback node (nd1).
Inventors:
DATE KOSHIRO (JP)
Application Number:
PCT/JP2019/006074
Publication Date:
September 12, 2019
Filing Date:
February 19, 2019
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/092; H03K3/356
Domestic Patent References:
| WO2017191799A1 | 2017-11-09 |
Foreign References:
| US20160063163A1 | 2016-03-03 | |||
| US20170179134A1 | 2017-06-22 | |||
| JP2011040826A | 2011-02-24 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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