Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/220983
Kind Code:
A1
Abstract:
Provided is a layout structure capable of suppressing variation in operation of a ROM memory cell using vertical nanowire (VNW) FETs. VNW FETs (T11-T14, T21-T24, T31-T34, T41-T44) provided in the ROM memory cell are configured so that: gates thereof are connected to word lines (WL, 21-24); bottoms thereof are connected to bit lines (BL, 11-14); and tops thereof are selectively connected to ground potential lines (41-44). Regardless of the data stored in the ROM memory cell, the bottoms of the VNW FETs provided in the ROM memory cell are connected to the bit lines (BL).
Inventors:
MORIWAKI SHINICHI (JP)
Application Number:
PCT/JP2019/018405
Publication Date:
November 21, 2019
Filing Date:
May 08, 2019
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/8246; G11C17/12; H01L27/10; H01L27/112; H01L29/786
Foreign References:
| US20150380547A1 | 2015-12-31 | |||
| JPH0461161A | 1992-02-27 | |||
| JP2000101039A | 2000-04-07 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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