Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/075540
Kind Code:
A1
Abstract:
According to the present invention, a nano sheet (21a) which is positioned in a P-type region to be furthest from an N-type region has a surface that is exposed from a gate wiring line (31), said surface being on the reverse side from the N-type region in the Y direction; a nano sheet (28a) which is positioned in the N-type region to be furthest from the P-type region has a surface that is exposed from a gate wiring line (33), said surface being on the reverse side from the P-type region in the Y direction; a nano sheet (23a) which is positioned in the P-type region to be closest to the N-type region has a surface that is exposed from the gate wiring line (31), said surface being on the N-type region side in the Y direction; and a nano sheet (26a) which is positioned in the N-type region to be closest to the P-type region has a surface that is exposed from the gate wiring line (33), said surface being on the P-type region side in the Y direction.
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Inventors:
IWAHORI JUNJI (JP)
Application Number:
PCT/JP2020/039062
Publication Date:
April 22, 2021
Filing Date:
October 16, 2020
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82; H01L21/8238; H01L27/088; H01L27/092
Domestic Patent References:
| WO2018030107A1 | 2018-02-15 |
Other References:
WECKX P., RYCKAERT J., PUTCHA V., DE KEERSGIETER A., BOEMMELS J., SCHUDDINCK P., JANG D., YAKIMETS D., BARDON M. G., RAGNARSSON L.: "Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3 nm", IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2 December 2017 (2017-12-02), pages 20.5.1 - 20.5.4, XP033306012
WECKX P., GUPTA M., ONIKI Y., RAGNARSSON L.-A., HORIGUCHI N., SPESSOT A., VERKEST D., RYCKAERT J., LITTA E. DENTONI, YAKIMETS D., : "Novel forksheet device architecture as ultimate logic scaling device towards 2nm", IEEE INTERNATIONAL ELECTRON DEVICES MEETINGS (IDEM), 7 December 2019 (2019-12-07), pages 36.5.1 - 36.5.4, XP033714586
WECKX P., GUPTA M., ONIKI Y., RAGNARSSON L.-A., HORIGUCHI N., SPESSOT A., VERKEST D., RYCKAERT J., LITTA E. DENTONI, YAKIMETS D., : "Novel forksheet device architecture as ultimate logic scaling device towards 2nm", IEEE INTERNATIONAL ELECTRON DEVICES MEETINGS (IDEM), 7 December 2019 (2019-12-07), pages 36.5.1 - 36.5.4, XP033714586
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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