Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/239681
Kind Code:
A1
Abstract:
A memory cell (C1) extends in the Y-direction and comprises a power supply wire (11) for supplying a power supply voltage VSS. A well tap cell (C2) comprises: a power supply wire (111, 212) extending in the Y-direction and electrically connected to the power supply wire (11) to supply the power supply voltage VSS; and a wire (171, 271) formed in an M1 wiring layer, and extending in the X-direction and electrically connected to the power supply wire (11) to supply the power supply voltage VSS. The well tap cell (C2) supplies the power supply voltage VSS to an N well(1) or a P-type substrate (2, 3) of the memory cell (C1).
Inventors:
HIROSE MASANOBU (JP)
Application Number:
PCT/JP2022/019374
Publication Date:
November 17, 2022
Filing Date:
April 28, 2022
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L27/11; G11C11/417; H01L21/3205; H01L21/768; H01L21/82; H01L21/8244; H01L23/522
Domestic Patent References:
| WO2019155559A1 | 2019-08-15 |
Foreign References:
| JP2013026594A | 2013-02-04 | |||
| JP2021061278A | 2021-04-15 | |||
| JP2001028401A | 2001-01-30 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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