Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND INDEX CALCULATION METHOD
Document Type and Number:
WIPO Patent Application WO/2011/161859
Kind Code:
A1
Abstract:
Disclosed are a semiconductor integrated circuit and an index calculation method that increase the speed of index calculation and reduce the circuit size and power consumption required when normalizing a plurality of data using a common index. Specifically disclosed is a semiconductor integrated circuit (50) that calculates a plurality of data indexes, when normalizing a plurality of data using a common index. The semiconductor integrated circuit (50) comprises: a bit sequence generation circuit (51) which generates second bit sequences that include a bit that takes a transition value which indicates that the values of adjacent bits differ, for each set of adjacent bits in a first bit sequence that makes up the data, or a non-transition value which indicates that the values of the adjacent bits do not differ; and an index calculation circuit that calculates a plurality of data indexes based on the position of transition value bits in a plurality of second bit sequences that are generated by a plurality of first bit sequences that make up each of the plurality of data.
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Inventors:
SHIBAYAMA, Atsufumi (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2011/002148
Publication Date:
December 29, 2011
Filing Date:
April 12, 2011
Export Citation:
Assignee:
NEC Corporation (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
International Classes:
G06F7/76
Attorney, Agent or Firm:
IEIRI, Takeshi (HIBIKI IP Law Firm, Asahi Bldg. 10th Floor 3-33-8, Tsuruya-cho, Kanagawa-ku, Yokohama-sh, Kanagawa 35, 〒2210835, JP)
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Claims: