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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, LATCH CIRCUIT, AND FLIP-FLOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2015/098017
Kind Code:
A1
Abstract:
Provided is a technology that is effective to power consumption reduction, while guaranteeing write operations to a semiconductor integrated circuit, and data holding performance. This semiconductor integrated circuit connected between a first node and a second node is configured from first to fourth transistors. The semiconductor integrated circuit is configured such that, when a signal of the second node changes, the fourth transistor is turned on, and a potential that is shifted by a threshold value of the fourth transistor from a third potential is applied to the gate of the second transistor. Consequently, data can be easily written to the semiconductor integrated circuit, and data holding performance can be guaranteed.

Inventors:
NAKANISHI, Kazuyuki
Application Number:
JP2014/006180
Publication Date:
July 02, 2015
Filing Date:
December 11, 2014
Export Citation:
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Assignee:
PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. (1-61, Shiromi 2-chome Chuo-ku, Osaka-sh, Osaka 07, 〒5406207, JP)
International Classes:
H03K3/356; H03K3/037; H03K19/0948
Foreign References:
JPH08316822A1996-11-29
JPH0677805A1994-03-18
JP2002026718A2002-01-25
JP2006115311A2006-04-27
JPH06164331A1994-06-10
JP2000278098A2000-10-06
JPH1093397A1998-04-10
JP2004080172A2004-03-11
JPH098612A1997-01-10
Attorney, Agent or Firm:
FUJII, Kentaro et al. (1-61, Shiromi 2-chome, Chuo-ku, Osaka-sh, Osaka 07, 〒5406207, JP)
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