Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING BUILT-IN MEMORY MOUNTED ON SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2004/081950
Kind Code:
A1
Abstract:
A cycle control section reads first data from a memory cell in an access cycle in which data is reliably read. A holding section temporarily holds the first data as expectation value data. The cycle control section, in a different access cycle from the first data access cycle, secondarily reads second data from the memory cell from which the first data is read. A comparing section compares the first data held in a holding circuit with the second data. When the result of the comparison shows that they are different from each other, a memory array is judged defective. The data read from the memory cell can be used as expectation data, the second data needs not to be compared with an expectation value outside the semiconductor integrated circuit. As a result, an expensive test device such as an LSI tester is not needed, reducing the built-in memory test cost.
More Like This:
Inventors:
KITAGAWA YASUHIRO (JP)
Application Number:
PCT/JP2003/002843
Publication Date:
September 23, 2004
Filing Date:
March 11, 2003
Export Citation:
Assignee:
FUJITSU LTD (JP)
KITAGAWA YASUHIRO (JP)
KITAGAWA YASUHIRO (JP)
International Classes:
G11C29/38; (IPC1-7): G11C29/00
Foreign References:
| JP2000156098A | 2000-06-06 | |||
| JPH06139786A | 1994-05-20 |
Attorney, Agent or Firm:
Furuya, Fumio (9th Floor 19-5, Nishishinjuku 1-chom, Shinjuku-ku Tokyo, JP)
Download PDF: