Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2002/099971
Kind Code:
A1
Abstract:
A semiconductor integrated circuit including a phase comparator circuit for a PLL or a DLL. The phase comparator circuit has no dead band, and the offset of the output current of a charge pump circuit is prevented. Therefore the locking accuracy of the whole PLL or DLL is improved. The semiconductor integrated circuit comprises a first circuit which activates a first phase difference signal according to the phase difference between first and second clock signals if the phase of the first clock signal is behind that of the second clock by a predetermined value and activates a second phase difference between the first and second clock signals if the phase of the first clock signal is ahead that of the second signal by a predetermined value, a second circuit which activates a first pulse signal if the edge of the first clock signal is behind that of the second clock signal and activates a second pulse signal if the edge of the first clock signal is ahead that of the second clock signal, a third circuit for combining the first phase difference signal with the first pulse signal, and a fourth circuit for combining the second phase difference signal with the second pulse signal.
Inventors:
NOGAMI KAZUTAKA (JP)
Application Number:
PCT/JP2002/005159
Publication Date:
December 12, 2002
Filing Date:
May 28, 2002
Export Citation:
Assignee:
THINE ELECTRONICS INC (JP)
NOGAMI KAZUTAKA (JP)
NOGAMI KAZUTAKA (JP)
International Classes:
H03D13/00; H03K5/04; H03K5/26; H03L7/089; (IPC1-7): H03K5/26; H03L7/00; H03K5/04
Foreign References:
| JPS50156969A | 1975-12-18 | |||
| JPH02164128A | 1990-06-25 | |||
| JPH05206845A | 1993-08-13 | |||
| JPH098655A | 1997-01-10 |
Attorney, Agent or Firm:
Oshima, Yumiko (Tokyo, JP)
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