Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/118119
Kind Code:
A1
Abstract:
Disclosed is memory having an internal power supply circuit mounted therein wherein at the time of supplying power to the memory by generating an internal power supply on the basis of an external power supply, power is stably supplied from the internal power supply, while reducing the circuit area and suppressing an increase of power consumption. In the memory, when the external power supply (102) is within a first voltage range, the internal power supply (103) is generated using only an internal step-down power supply block (101), and when the external power supply (102) is within a second voltage range, which is lower than the first voltage range, the internal power supply (103) is generated using an internal step-up power supply block (112) in addition to the internal step-down power supply block (101).
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Inventors:
NAKAMURA, Toshihiro (())
中村敏宏 (())
中村敏宏 (())
Application Number:
JP2011/000773
Publication Date:
September 29, 2011
Filing Date:
February 10, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NAKAMURA, Toshihiro (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NAKAMURA, Toshihiro (())
International Classes:
H01L21/822; G11C11/4074; H01L21/8242; H01L27/04; H01L27/10; H01L27/108; H02M3/00
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims: