Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/031330
Kind Code:
A1
Abstract:
This semiconductor integrated circuit is provided with: a phase synchronization circuit that is synchronized to a reference clock signal and that generates a synchronous clock signal in which the reference clock signal is multiplied; an edge detection circuit that detects an edge at which the signal waveform of the reference clock signal changes at the timing of the synchronous clock signal and that outputs an edge detection signal representing the timing at which the edge was detected; and a clock division circuit that is reset at a timing corresponding to the edge detection signal and that generates a divided clock signal in which the synchronous clock signal is divided.
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Inventors:
MURATA YUTAKA (JP)
UENO AKIRA (JP)
UENO AKIRA (JP)
Application Number:
PCT/JP2018/029922
Publication Date:
February 13, 2020
Filing Date:
August 09, 2018
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
H03K5/00; G06F1/10
Foreign References:
| JP2011004248A | 2011-01-06 | |||
| JP2015080049A | 2015-04-23 | |||
| JPS61264911A | 1986-11-22 | |||
| JP2011160097A | 2011-08-18 | |||
| US20170134031A1 | 2017-05-11 |
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
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