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Title:
SEMICONDUCTOR INTEGRATED OPTICS ELEMENT AND PRODUCTION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2019/172089
Kind Code:
A1
Abstract:
The purpose of the invention is to prevent increases in production costs, without additional inspection steps, when providing semiconductor integrated optics elements (AXEL) with higher output. The invention provides a semiconductor integrated optics element production method comprising: the step of forming a semiconductor wafer on which a plurality of semiconductor integrated optics elements are two dimensionally arranged with the optical axis directions thereof being aligned, each semiconductor integrated optics element comprising a DFB laser, EA modulator, and SOA monolithically integrated on the same substrate and disposed in the order of DFB laser, EA modulator, and SOA in the light output direction; the step of cleaving the semiconductor wafer in a plane orthogonal to the light output direction into a semiconductor bar comprising a plurality of the semiconductor integrated optics elements arranged one-dimensionally in an orthogonal direction to the light output direction with adjacent semiconductor integrated optics elements sharing the same cleavage end face as a light output surface; the step of inspecting each of the semiconductor integrated optics elements on the semiconductor bar by energizing and driving the same via a connection wiring section electrically connecting an electrode of the SOA to an electrode of the DFB laser; and the step, after the inspection, of separating each of the semiconductor integrated optics elements on the semiconductor bar at a boundary line with the adjacent semiconductor integrated optics element so that the connection wiring section connecting the electrode of the SOA to the electrode of the DFB laser is cut and the semiconductor integrated optics elements are electrically separated from each other.

Inventors:
SHINDO TAKAHIKO (JP)
FUJIWARA NAOKI (JP)
SANO KIMIKAZU (JP)
ISHII HIROYUKI (JP)
MATSUZAKI HIDEAKI (JP)
YAMADA TAKASHI (JP)
HORIKOSHI KENGO (JP)
Application Number:
PCT/JP2019/007910
Publication Date:
September 12, 2019
Filing Date:
February 28, 2019
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H01S5/042; H01S5/026; H01S5/12; H01S5/227; H01S5/50
Domestic Patent References:
WO2016136183A12016-09-01
Foreign References:
JP2013258336A2013-12-26
JP2012019248A2012-01-26
JP2005197511A2005-07-21
JP2017228654A2017-12-28
JPS6022391A1985-02-04
JP2008294124A2008-12-04
US20040105476A12004-06-03
JP2013258336A2013-12-26
Other References:
W KOBAYASHI ET AL.: "Novel approach for chirp and output power compensation applied to a 40-Gbit/s EADFB laser integrated with a short SOA", OPT. EXPRESS, vol. 23, no. 7, April 2015 (2015-04-01), pages 9533 - 9542
Attorney, Agent or Firm:
TANI & ABE, P.C. (JP)
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